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PRELIMINARY
XRT79L71
182
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
For more information the Analog LOS Detector, and the LOS Defect Declaration criteria, please see
Section4.3.1.2.3
Configuration Options associated with the AGC Block - Operating the Receive DS3/E3 LIU
Block in the Receive Monitor Mode
For some test equipment applications, it is desirable for a given piece of equipment to be able to receive a
Monitor signal. In this case, we define a Monitor signal as a DSX-3 signal that has been attenuated by 20dB of
flat loss.
In order to configure the Receive DS3/E3 LIU Block to be capable of properly receiving (and monitoring) a
Monitor signal, the user must configure it to operate in the Receive Monitor Mode. The user can configure the
XRT79L71 to operate in the Receive Monitor Mode by setting Bit 1 (Receive Monitor Mode Enable), within the
LIU Receive Control Register, to "1" as depicted below.
4.3.1.3
The Receive Equalizer Block
As a given pulse within a DS3 or E3 line rate signal travels from its source to the destination terminal via
coaxial cable, it will experience a frequency-dependent loss, in which the high-frequency portions of this signal
are more greatly attenuated than are the lower-frequency components of the signal.
The result of this
frequency-dependent loss is manifested by a change in shape of a given pulse within this DS3 or E3 line
signal.
More specifically, one will typically note that (as a given pulse travels along the communication
medium) fast rising and falling edges give way to slower rising and falling edge. Pulses that originally of the
square-wave shape (at the output of the source terminal) become less square and more rounded in shape as
they travel along the coaxial cable. If the DS3 data-stream travels a sufficiently long distance, then an entity
that is responsible for properly receiving a given incoming DS3 signal, will have trouble receiving this particular
signal, due to phenomenon such as ISI (Inter-Symbol Interference).
The purpose of the Receive Equalizer block is to compensate for this frequency-dependent attenuation that
occurs within a DS3 or E3 signal, traveling via coaxial cable.
In essence, the Receive Equalizer block
accomplishes this by applying higher gain to higher frequency signals, than it does for lower frequency signals.
The Register Set, within the XRT79L71, permits the user to either enable or disable the Receive Equalizer,
within the Receive DS3/E3 LIU Block. In general, we strongly recommend that the user ALWAYS ENABLE the
Receive Equalizer block for all applications.
The user can enable the Receive Equalizer block by setting Bit 0 (Receive Equalizer Enable), within the LIU
Receive Control Register, to "1" as depicted below.
LIU Receive Control Register (Address = 0x1305)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Disable
DLOS
Detector
Disable
ALOS Detec-
tor
Unused
LOSMUT
Enable
Receive
Monitor
Mode Enable
Receive
Equalizer
Enable
R/O
R/W
R/O
R/W
0
1