![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_160.png)
XRT79L71
PRELIMINARY
145
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
FIGURE 61. ILLUSTRATION OF THE NEAR-END RECEIVE DS3/E3 FRAMER BLOCK RECEIVING A PROPER DS3 SIGNAL
FROM THE
REMOTE TERMINAL EQUIPMENT (E.G., THE LOS DEFECT CONDITION IS CLEARED)
Transmit Payload
Data Input
Interface Block
Transmit DS3/E3
Framer Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
Receive DS3/E3
Framer Block
Receive Payload
Data Output
Interface Block
Microprocessor
Interface
TxSer
TxNib[3:0]
TxInClk
MOTO
D[7:0]
A[8:0]
IntB*
CSB*
RdB_DS
WrB_RW
Rdy_Dtck
Reset*
ALE_AS
RxSer
RxNib[3:0]
RxOutClk
Tx LAPD Buffer/
Controller
Rx LAPD Buffer/
Controller
Transmit Overhead
Input
Interface Block
Receive Overhead
Output
Interface Block
TxOHClk
TxOHIns
TxOHInd
TxOH
TxOHEnable
TxOHFrame
TxNibClk
TxFrame
RxNibClk
RxFrame
RxOHFrame
RxOH
RxOHClk
RxOHEnable
RxOHInd
Transmit
DS3/E3
LIU Block
Transmit
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
TTIP
TRING
RTIP
RRING
Only one JA exists.
Can be configured in
Tx or Rx Path
No Defects
Declared