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PRELIMINARY
XRT79L71
112
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Equipment must set this particular bit-field to "0". The System-Side Terminal Equipment begins this process by
implementing the following two tasks concurrently.
TASK 1 - The System-Side Terminal Equipment asserts the TxOHIns input pin by setting it "High".
TASK 2 - The System-Side Terminal Equipment sets the TxOH input pin to "0".
After the System-Side Terminal Equipment has executed these two tasks, the XRT79L71 will sample the
TxOHIns input pin being "High" and the TxOH input pin being set "Low" during second rising edge of TxInClk
after TxOHFrame and TxOHEnable were initially sampled "High" at Clock Edge # 2, in Figure 47. Once the
XRT79L71 has sampled these two signals, it will then insert a "0" into the very first X bit-position, within the
outbound DS3 frame.
Upon detection of the very next rising edge of the TxInClk clock signal (designated as Clock Edge # 3, in
Figure 47), the System-Side Terminal Equipment will negate or de-assert the TxOHIns input signal (e.g.,
toggle it "Low") and cease inserting data into the Transmit Overhead Data Input Interface block until it samples
the TxOHEnable output pulsing "High" eight more times (depicted in Figure 47 as TxOHEnable Pulse # 8).
According to Table 21, the occurrence of TxOHEnable Pulse # 8 indicates that the XRT79L71 is just about
ready to process the second X bit, within the outbound DS3 frame. In order to facilitate this transmission of the
FERF indicator, this particular X bit must also be set to "0". The System-Side Terminal Equipment begins this
process by implementing the following two tasks concurrently.
TASK 1 - The System-Side Terminal Equipment asserts the TxOHIns input pin by setting it "High".
TASK 2 - The System-Side Terminal Equipment sets the TxOH input pin to "0".
After the System-Side Terminal Equipment has executed these two tasks, the XRT79L71 will sample the
TxOHIns input pin being "High" and the TxOH input pin being set "Low" during the second rising edge TxInClk
after TxOHEnable Pulse # 8 was sampled "High. Once the XRT79L71 has sampled this signal, it will then
insert a "0" into the second X bit-position within the outbound DS3 frame.
Upon detection of the very next rising edge of the TxInClk clock signal (designated as Clock Edge # B, in
Figure 47), the System-Side Terminal Equipment will negate or de-assert the TxOHIns input signal (e.g.,
toggle it "Low") and cease inserting data into the Transmit Overhead Data Input Interface block until it samples
the TxOHEnable and the TxOHFrame output signals pulsing "High" simultaneously. Afterwards, the System-
Side Terminal Equipment will repeat all of the steps that have been outlined in this case study.
4.2.3
TRANSMIT FEAC CONTROLLER BLOCK
The Transmit FEAC Controller Block is the fourth functional block within the Transmit Direction of the
XRT79L71 that we will discuss for Clear-Channel Framer Applications. Figure 48 presents an illustration of the
Transmit Direction circuitry whenever the XRT79L71 has been configured to operate in the DS3 Clear-Channel
Framer Mode, with the Transmit FEAC Controller block highlighted.