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XRT79L71
PRELIMINARY
83
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
expected to begin the transmission of the contents of the very next outbound DS3 frame, via the
DS3_Data_Out[3:0] output or TxNib[3:0] input pins.
The Transmit Payload Data Input Interface block's handling of DS3 Overhead bits when configured to
operate in the Nibble-Parallel Mode
If one reviews the DS3 framing formats for both M13 and C-bit Parity in Figure 14 and Figure 15, one will
quickly note that the DS3 framing format is a bit-oriented framing format. More specifically, each of the DS3
framing formats consists of multiple strings of 84 consecutive bits of payload data that are separated from each
other by a DS3 overhead bit. As a consequence, there will never be a case in which the Transmit Payload
Data Input Interface, within the XRT79L71, will be processing a DS3 overhead nibble. In other words, the
TxOH_Ind output pin has no meaning and will NOT be active whenever the XRT79L71 is configured to operate
in both the DS3 and Nibble-Parallel Modes.
Whenever the user configures the Transmit Payload Data Input Interface to operate in the Nibble-Parallel
Mode, then it will only handle or process DS3 payload bits. This statement brings us to the next topic.
The Frequency of TxNibClk for DS3, Nibble-Parallel Mode Operation
As mentioned above, whenever the Transmit Payload Data Input Interface has been configured to operate in
the Nibble-Parallel Mode, it will NOT process the DS3 overhead bits. Only DS3 payload data is processed
through the Transmit Payload Data Input Interface (e.g., via the TxNib[3:0] input pins). As a consequence, the
frequency of the TxNibClk signal will NOT simply be 44.736MHz/4 or 11.184MHz.
If we were to look at this issue another way, we would recall that each DS3 frame consists of 4760 bits. Of
these bits, 56 are overhead bits and the remaining 4704 bits are payload bits. This means that there are 4704
bits/4 = 1176 nibbles of payload bits within each DS3 frame.
The frame repetition rate (for DS3) is 9.398kHz. Therefore, if one performs the following multiplication:
9398 Frames/sec 1176 Nibble/Frame = 11.052MHz (for the Average Frequency of the TxNibClk output
signal).
How 1176 Clock Edges within the TxNibClk output signal are distributed throughout a DS3 frame.
In general, for 1120 TxNibClk periods, the instantaneous frequency of the TxNibClk output clock signal will be
11.184MHz (e.g., each of these TxNibClk clock periods will corresponding to exactly 4 RxOutClk clock
periods). However, for the remaining 56 of these TxNibClk periods, the periods of these clock signals will be
lengthened to five (5) of these RxOutClk clock periods.
For this reason, if one were to monitor the TxNibClk signal via a scope the user would notice what appears to
be a considerable amount of jitter within this particular clock signal.
Figure 37 presents an illustration of the System-Side Terminal Equipment/Transmit Payload Data Input
Interface signals for Mode 4 Operation.