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PRELIMINARY
XRT79L71
564
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
TABLE 70: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE BLOCK
NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION
RxOH
C7
O
Receive Overhead Data Output Interface block - Data Output pin:
How to sample this output pin depends upon whether "Method 1" (see
for extracting data from the "Receive Overhead Data Output Interface block.
If Method 1 is used:
The XRT79L71 outputs the overhead bits, within the incoming E3 data-
stream, via this output pin. The Receive Overhead Data Output Interface
block will output a given bit, upon the falling edge of RxOHClk. Hence, the
"System-Side Terminal Equipment" should be designed (or configured) to
sample the data, at this pin, upon the rising edge of RxOHClk.
If Method 2 is used:
The XRT79L71 outputs the overhead bits, within the incoming E3 data-
stream, via this output pin. The Receive Overhead Data Output Interface
block will assert the "RxOHEnable" output pin (for one "RxClk" period)
whenever the data, residing on the "RxOH" output pin has become stable
and is safe for "sampling". In this case, the user should design (or config-
ure) the System-Side Terminal Equipment to sample and latch the "RxOH"
data upon the falling edge of "RxClk" coincident to whenever the "RxOHEn-
able" output pin is sampled "high".
The XRT79L71 will always output the E3 overhead bits via this output pin.
There are no external input pins or register bits settings available that will
disable this output pin.
RxOHClk
A7
O
Receive Overhead Data Output Interface block - Clock Output pin:
This output pin is only used if "Method 1" is employed to extract overhead
data from the "Receive Overhead Data Output Interface" port (see
-PAGE 565., below). The XRT79L71 will output the overhead bits (within the
incoming E3 data-stream), via the "RxOH" output pin, upon the falling edge
of this particular clock signal. As a consequence, the "System-Side Termi-
nal Equipment" should be designed (or configured) to sample the data, at
this pin, upon the rising edge of RxOHClk.
NOTE: This output clock signal is always active.