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PRELIMINARY
XRT79L71
494
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: As the user writes in the values for these remaining fifteen (15) registers, it is imperative that the user make sure
that the MSB (Most Significant Bit) position within each of these registers is set to "0". If the user sets any of the
MSB's within these remaining 15 registers to "1" then the remote terminal equipment will not be able to properly
receive this particular Trail-Trace Message.
Once the user has executed all of these steps, then the Transmit Trail-Trace Message Controller will
immediately begin to do its job, by writing the appropriate values into the TR byte-positions, within each
outbound E3 frame.
For information on how the Receive Trail-Trace Message Controller handles incoming Trail-Trace Messages,
as well has how to use the Receive Trail-Trace Message Controller, please see SEE”RECEIVE TRAIL- 6.2.5
TRANSMIT SSM CONTROLLER BLOCK
The Transmit SSM Controller block is the fifth functional block within the Transmit Direction of the XRT79L71
that we will discuss for E3, Clear-Channel Framer Applications. Figure 230 presents an illustration of the
Transmit Direction circuitry whenever the XRT79L71 has been configured to operate in the E3, ITU-T G.832
Clear-Channel Framer Mode, with the Transmit Trail Trace Message Controller block highlighted.
Transmit E3 Trail-Trace Message Byte 15 Register - G.832 (Address = 0x1146)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxTTB_Byte_15
R/W
0
N6
N5
N4
N3
N2
N1
N0
Transmit E3 Trail-Trace Message Byte 16 Register - G.832 (Address = 0x1147)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxTTB_Byte_16
R/W
0
P6
P5
P4
P3
P2
P1
P0