參數(shù)資料
型號: μPD30181
廠商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 20/68頁
文件大小: 270K
代理商: ΜPD30181
20
μ
PD30700,30700L,30710
2.3 System Control Coprocessor (CP0)
The CP0 registers/CP0 instructions access the TLB and cache. Manipulating a mode in which the V
R
10000 is used,
exceptions, and interrupts are also controlled by the CP0. In addition, the CP0 also has a test/debug function.
2.3.1 CP0 registers
All the CP0 registers that can be used with the V
R
10000 are listed below. Writing or reading an unused register
(RFU) is undefined.
Figure 2-3. CPU0 Registers and TLB
Remark
“*” indicates a register number.
Entry Lo0
2*
Entry Hi
10*
Entry Lo1
3*
Index
0*
Random
1*
Page mask
5*
Wired
6*
Config
16*
Watch Hi
19*
ECC
26*
PC
25*
Frame mask
21*
TLB
63
0
0
127/255
("Safe" entry)
Context
4*
BadVAddr
8*
Count
9*
Compare
11*
Cause
13*
Status
12*
EPC
14*
PRld
15*
Watch Lo
18*
X context
20*
LLAddr
17*
Tag Hi
29*
Cache error
27*
Diagnosis
22*
Tag Lo
28*
Error EPC
30*
Registers used by memory management system
Registers used for exception processing
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