參數(shù)資料
型號: μPD30181
廠商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 41/68頁
文件大小: 270K
代理商: ΜPD30181
41
μ
PD30700,30700L,30710
6. INSTRUCTION SET
The instructions of the V
R
10000 consists of 1 word (32 bits) located at a word boundary, and come in three formats
as shown in Figure 6-1. Because only three types of instructions are provided, decoding instructions is simplified.
Complicated operations and addressing modes that are not so often used are implemented by a compiler.
6.1 Instruction Formats
The instruction formats of the V
R
10000 are shown below.
Figure 6-1. CPU Instruction Format
6.2 CPU Instruction Set List
The CPU instructions of the V
R
10000 can be classified into an instruction set common to all the V
R
series processors
(ISA: Instruction Set Architecture), instruction set that is executed by the V
R
4000 series and V
R
10000 series (expanded
ISA), and system control coprocessor instruction set. Tables 6-1 through 6-4 list each instruction set.
31
26 25
21 20
16 15
0
op
rs
rt
immediate
op
target
op
rs
rt
rd
sa
funct
31
26 25
0
31
26 25
21 20
16 15
0
11 10
6 5
I - type (immediate format)
J - type (jump format)
R - type (register format)
op
rs
rt
immediate
target
rd
sa
funct
6-bit instruction code
5-bit source register specifier
5-bit target (source/destination) register, or branch condition
16-bit immediate value, branch displacement, or address displacement
26-bit unconditional branch target address
5-bit destination register specifier
5-bit shift amount
6-bit function field
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