參數(shù)資料
型號(hào): μPD30181
廠商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁(yè)數(shù): 28/68頁(yè)
文件大?。?/td> 270K
代理商: ΜPD30181
28
μ
PD30700,30700L,30710
Figure 2-12. Outline of Address Translation
TLB entries are read or written by loading/storing the TLB entry indicated by the index register and the random
register from or to the entry Hi, entry Lo1, Entry Lo0, and page mask registers.
Figure 2-13 outlines TLB manipulation.
Figure 2-13. Outline of TLB Manipulation
y+8
y+1 y
x+1 x
0
x–1
63
0
ASID
VPN
Offset
Virtual address
<1>
<2>
<3>
Selector
<4>
40
x x–1
0
TLB
x = 12, 14, 16, 18, 20, 22, 24
y = 31 (in 32-bit mode)
63 (in 64-bit mode)
Physical address
<1> A virtual address page number (VPN) is
compared with VPN in TLB.
<2> If the two VPNs coincide, a page frame number
(PFN) indicating the high-order bits of a physical
address is output to the selector.
<3> If the least significant bit of VPN is 0, an even
page is selected; if it is 1, an odd page is selected.
The selected page is output to the high-order bits
of the physical address.
<4> The offset is output to the low-order bits of the
physical address without via TLB.
Entry Lo0 register
Page mask register
Entry Lo1 register
Entry Hi register
Index
register
Random register
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