參數(shù)資料
型號: μPD30181
廠商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 49/68頁
文件大小: 270K
代理商: ΜPD30181
49
μ
PD30700,30700L,30710
6.4 Delay of Instruction
(1) Delay of integer instructions
Table 6-9 shows execution delay of the integer instructions.
For details of each instruction, refer to
V
R
5000, V
R
10000 User’s Manual – Instruction
.
Table 6-9. Integer Operation Instruction Delay Time
Instruction Type
Execution Unit
PClk
Repeat Rate
Remark
ADD, SET, SUB, Logical
ALU1, ALU2
1
1
MFHI, MTHI, MFLO, MTLO
1
1
Shift, LUI
ALU1
1
1
Conditional Branch
1
1
Conditional Move
1
1
MULT
ALU2
5/6
6
Delay of LO/HI
MULTU
6/7
7
Delay of LO/HI
DMULT
9/10
10
Delay of LO/HI
DMULTU
10/11
11
Delay of LO/HI
DIV, DIVU
34/35
35
Delay of LO/HI
DDIV, DDIVU
66/67
67
Delay of LO/HI
Load (except for CP1 instruction)
Load/store
2
1
In the case of cache hit
Store
1
In the case of cache hit
(2) Delay of floating-point instructions
Table 6-10 shows the execution delay of the floating-point instruction.
For details of each instruction, refer to
V
R
5000, V
R
10000 User’s Manual – Instruction
.
Table 6-10. Floating-Point Instruction Delay Time
Instruction Type
Execution Unit
PClk
Repeat Rate
Remark
MTC1, DMTC1
ALU1
3
1
ADD, SUB, ABS, NEG, ROUND,
TRUNC, CEIL, FLOOR, C.cond
Fp adder
2
1
CVT.S.W, CVT.S.L
4
2
Average value of repeat rate
CVT (other than above)
2
1
MUL
Fp multiplier
2
1
MFC1, DMFC1
2
1
Conditional MOVE/CVT.S.L
2
1
DIV.S, RECIP.S
12
14
DIV.D, RECIP.D
19
21
SQRT.S
18
20
SQRT.D
33
35
RSQRT.S
30
20
RSQRT.D
52
35
MADD
Fp adder + Fp
multiplier
2/4
1
“2” if other MADD instruction uses operation
result
LWC1, LDC1, LWXC1, LDXC1
Load/store
3
1
In the case of cache hit
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