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參數(shù)資料
| 型號(hào)： | μPD30181 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit RISC Microprosessor(64位RISC微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ΜPD30181 |
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32
μ
PD30700,30700L,30710
4. INTERFACE
4.1 System Interface
The I/O timing of the V
R
10000 is as follows:
Output starts changing at the rising edge of SysClk.
Input is latched at the rising edge of SysClk.
The following two buses are used for system interfacing.
SysAD (63:0) : This bus transfers addresses and data.
SysCmd (11:0) : This bus transfers command data identifiers.
Both SysAD and SysCmd are bidirectional buses and are driven by the V
R
10000 or external agent. Depending
on the direction in which they are driven, these buses are in the following two statuses.
Master status : Driven by the V
R
10000 to issue a processor request.
Slave status
: Driven by the external agent to issue an external request.
The following two cycles are used depending on the information included in the SysAD bus.
Address cycle : A valid address is included in the SysAD bus.
Data cycle
: Valid data is included in the SysAD bus.
Next, the interface control signals are briefly explained.
SysReq
: Signal used by the V
R
10000 to request the right to use the system interface.
SysGnt
: Signal used by the external agent to grant the V
R
10000 the right to use the system interface.
SysRel
: Asserted active when the master of the system interface releases the right of use.
SysRdRdy
: Indicates that the external agent is ready to accept a processor read request and upgrade
request.
SysWrRdy
: Indicates that the external agent is ready to accept a processor write request and processor
eliminate request.
SysVal
: Asserted active when the master of the system interface outputs valid data to the SysAD and
SysCmd buses.
SysState (2:0) : Signal used by the V
R
10000 to issue a coherent status request.
SysResp (4:0) : Signal used by the external agent to issue an external end response.
SysGblPerf
: Signal used by the external agent to indicate that all processor requests have been completed.
4.1.1 Setting operating frequency of system interface
The V
R
10000 can select the operating frequency of the system interface.
The clock (PClk) for pipeline operation is generated based on the clock (SysClk) input from an external source.
The factor by which SysClk is multiplied to generate PClk is set by using the BTMC interface at reset. For details,
refer to
SysAD (9:12) in
Table 4-1 Mode Setting in Boot Time Mode
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| PD302 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | DOME-5.0 |
| PD3032 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Li-ion Rechargeable Battery |
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| PD307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | LED-2A |
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