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參數(shù)資料
| 型號(hào)： | μPD30181 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit RISC Microprosessor(64位RISC微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁(yè)數(shù)： | 39/68頁(yè) |
| 文件大?。?/td> | 270K |
| 代理商： | ΜPD30181 |
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39
μ
PD30700,30700L,30710
5. INTERNAL/EXTERNAL CONTROL FUNCTIONS
5.1 Reset Function
The following three types of reset functions are available:
Power-ON reset
Cold reset
Software reset
Cold reset and software reset are executed with the power turned on.
As a result of reset, the internal status is initialized. However, software reset does not affect the internal clock and
secondary cache clock.
5.1.1 Power-ON reset and cold reset
Power-ON reset and cold reset are executed when the SysGnt and SysRespVal signals are deasserted inactive
and the SysReset signal is asserted active. During reset, 64-bit data is received from the mode bit, and the internal
status of the processor is initialized (for further information, refer to
4.5 BTMC Interface
).
5.1.2 Software reset
Software reset is executed when the SysGnt and SysRespVal signals are deasserted inactive and the SysReset
signal is asserted active. As a result, all the statuses of the external interface are initialized, but the internal clock
and secondary cache clock continues operating. Like the primary and secondary cache, the contents of the CP0 and
FPU registers are retained.
5.2 Interrupt Functions
There are two major types of interrupt requests:
Maskable interrupt request
Non-maskable interrupt (NMI) request
(1) Maskable interrupt requests
These interrupts can be masked by using the status register (each interrupt can be serviced independently,
or all interrupts can be serviced in batch).
There is no priority assigned to the interrupts.
(a) Hardware interrupt requests (five sources)
These interrupts are acknowledged when the corresponding external interrupt request is issued.
(b) Software interrupt requests (two sources)
These interrupts are acknowledged when the IP0 and IP1 bits of the cause register are set.
(c) Timer interrupt request (1 source)
This interrupt is acknowledged when the IP7 bit of the cause register is set because the value of the count
register has become equal to the value of the compare register, or when one of the two performance
counters has overflown.
(2) NMI request (1 source)
This is an interrupt request that cannot be masked and is acknowledged when the SysNMI signal is asserted
active.
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| μPD30200 | High-Performance, 64-Bit RISC Microprosessor(高性能64位RISC微處理器) |
| μPD30700L | 64-Bit Microprocessor(64位RISC微處理器) |
| μPD30700 | 64-Bit Microprocessor(64位RISC微處理器) |
| μPD30710 | 64-Bit Microprocessor(64位RISC微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PD302 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | DOME-5.0 |
| PD3032 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Li-ion Rechargeable Battery |
| PD306 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | DOME-3.0 |
| PD307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | LED-2A |
| PD308 | 制造商:NIEC 制造商全稱:Nihon Inter Electronics Corporation 功能描述:DIODE MODULE 30A/800V |
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