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參數(shù)資料
| 型號： | μPD30181 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit RISC Microprosessor(64位RISC微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ΜPD30181 |
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38
μ
PD30700,30700L,30710
4.6 DSD (Delay Speculative Dirty) Mode (V
R
12000 only)
The DSD (Delay Speculative Dirty) mode prevents a dirty bit from being set by speculative storing.
Bit 24 in the boot mode coincides with bit 24 of the config register and sets the DSD mode in the kernel mode and
supervisor mode. However, the DSD mode can be also executed in the user mode by setting bit 24 of the status
register. Bit 24 of the config register is read-only and can be set only during boot time.
When the DSD mode has been set, the dirty bit of the secondary cache block of the V
R
12000 are not set until the
store instruction has become the oldest instruction in the active list and ready to be executed (the dirty bit may be
set by an interrupt (and the store instruction is no longer in the speculative status), but the store instruction is not
immediately completed).
4.6.1 DSD mode delay
The DSD mode delays setting of a dirty bit but slightly slows down the processing speed. This slowdown occurs
each time a block is refilled from the main memory if it is necessary to set the dirty bit. It takes 10 cycles to set the
dirty bit. During this time, the processor executes the other instructions in parallel.
Once a block becomes dirty in the secondary cache, this mode does not affect the performance.
4.6.2 Secondary cache status in DSD mode
The secondary cache in the DSD mode enters the Clean Exclusive status if a miss hit occurs when the store
instruction is no longer the oldest instruction in the pipeline.
Because the cache is upgraded to the Clean Exclusive status immediately after a hit occurs in a line in the Shared
status, bus manipulation is started in the speculative status (the processing speed relatively slows down).
4.6.3 Other features
The V
R
12000 delays loading of the non-coherent cache until this instruction becomes the oldest, regardless of the
DSD mode. This is because speculative loading that accesses an address of the xkphys area not mapped as a non-
coherent cache may send data to the secondary cache without appropriate coherency check.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| μPD30210 | 64-Bit MIPS RISC Microprocessor(64位MIPS RISC 微處理器) |
| μPD30200 | High-Performance, 64-Bit RISC Microprosessor(高性能64位RISC微處理器) |
| μPD30700L | 64-Bit Microprocessor(64位RISC微處理器) |
| μPD30700 | 64-Bit Microprocessor(64位RISC微處理器) |
| μPD30710 | 64-Bit Microprocessor(64位RISC微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PD302 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | DOME-5.0 |
| PD3032 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Li-ion Rechargeable Battery |
| PD306 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | DOME-3.0 |
| PD307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHOTOTRANSISTOR | DARLINGTON | 800NM PEAK WAVELENGTH | 30M | LED-2A |
| PD308 | 制造商:NIEC 制造商全稱:Nihon Inter Electronics Corporation 功能描述:DIODE MODULE 30A/800V |
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