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參數(shù)資料
| 型號： | 20726 |
| 英文描述： | 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology |
| 中文描述： | 3DNow！？技術(shù)手冊的AMD - K6處理器多媒體技術(shù) |
| 文件頁數(shù)： | 10/120頁 |
| 文件大?。?/td> | 1284K |
| 代理商： | 20726 |
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AMD-K6 Processor Multimedia Technology
AMD-K6 MMX Enhanced Processor Multimedia Technology
20726D/0—January 2000
Preliminary Information
Executing MMX
Instructions
A programmer must approach the use of MMX instructions
differently, based on whether the code being developed is at
the system level or at the application level. The details of these
differences are discussed in
“Programming Considerations” on
page 9
.
Before using the MMX instructions, the programmer must use
the CPUID instruction to determine if the processor supports
multimedia technology. See the
AMD Processor Recognition
Application Note
, order# 20734, for more information.
Function 1 (EAX=1) of the AMD-K6 processor CPUID
instruction returns the processor feature bits in the EDX
register. Software can then test bit 23 of the feature bits to
determine if the processor supports the multimedia technology.
If bit 23 is set to 1, MMX instructions are supported. All
AMD-K6 processors have bit 23 set. Once it is determined that
multimedia technology is supported, subsequent code can use
the MMX instructions. Alternatively, the AMD 8000_0001h
extended CPUID function can be used to test whether the
processor supports multimedia technology.
After a module of MMX code has executed, the programmer
must empty the MMX state by executing the EMMS command.
Because the MMX registers share the floating-point registers,
an instruction is needed to prevent MMX code from interfering
with floating-point. The EMMS command clears the multimedia
state and resets all the floating-point tag bits. Emptying the
MMX state sets the floating-point tag bits to empty (all ones),
which marks the MMX/FP registers as invalid and available.
Register Set
The AMD-K6 processor implements eight new 64-bit MMX
registers. These registers are mapped on the floating-point
registers. As shown in Figure 1 on page 5, the new MMX
instructions refer to these registers as mmreg0 to mmreg7.
Mapping the new MMX registers on the floating-point stack
enables backwards compatibility for the register saving that
must occur as a result of task switching.
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