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參數(shù)資料
| 型號： | 20726 |
| 英文描述： | 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology |
| 中文描述： | 3DNow??？技術(shù)手冊的AMD - K6處理器多媒體技術(shù) |
| 文件頁數(shù)： | 49/120頁 |
| 文件大?。?/td> | 1284K |
| 代理商： | 20726 |
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MMX Instruction Set
43
20726D/0—January 2000
AMD-K6 MMX Enhanced Processor Multimedia Technology
Preliminary Information
PAND
mnemonic
opcode
description
PAND mmreg1, mmreg2/mem64
0F DBh
AND 64-bit values
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
The PAND instruction operates on the 64-bit source and destination operands to
complete a bitwise logical AND. The results are stored in the destination operand. If
the corresponding bits in the source and destination operands both equal 1, the
resulting bit is 1 in the destination. If either bit in the source or destination operands
equals 0, the resulting bit is 0 in the destination.
The PAND instruction can be used to extract operands from packed fields based on
the masks that are produced by the compare instructions—PCMPEQ and PCMPGT.
This technique can eliminate branch prediction overhead in MMX routines.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate MMX instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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