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參數(shù)資料
| 型號(hào)： | 20726 |
| 英文描述： | 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology |
| 中文描述： | 3DNow！？技術(shù)手冊(cè)的AMD - K6處理器多媒體技術(shù) |
| 文件頁(yè)數(shù)： | 11/120頁(yè) |
| 文件大小： | 1284K |
| 代理商： | 20726 |
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AMD-K6 Processor Multimedia Technology
5
20726D/0—January 2000
AMD-K6 MMX Enhanced Processor Multimedia Technology
Preliminary Information
Figure 1.
MMX Registers
Aliasing the MMX registers onto the floating-point stack
registers provides a safe way to introduce this new technology.
Instead of needing to modify operating systems, new MMX
applications can be supported through device drivers, MMX
libraries, or DLL files. See the
Programming Considerations
section of this document for more information.
Current operating systems have support for floating-point
operations. Using the floating-point registers for MMX code is
an ingenious way of implementing automatic support for MMX
instructions. Every time the processor executes an MMX
instruction, all the floating-point register tag bits are set to zero
(00b=valid). Setting the tag bits after every MMX instruction
prevents the processor from having to perform extra tasks.
These extra tasks are normally executed on floating-point
registers when the Tag field is something other than 00b.
If a task switch occurs during an MMX or floating-point
instruction, the Control Register (CR0) Task Switch (TS) bit is
set to 1. The processor then generates an interrupt 7 (int 7
Device Not Available) when it encounters the next
floating-point or MMX instruction, allowing the operating
system to save the state of the MMX/FP registers.
TAG BITS
63
0
mmreg0
mmreg7
mmreg1
mmreg6
mmreg5
mmreg2
mmreg3
mmreg4
xx
xx
xx
xx
xx
xx
xx
xx
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