參數(shù)資料
型號(hào): 20736
英文描述: Enhanced Am486DX Family Data Sheet? 1.87MB (PDF)
中文描述: 增強(qiáng)Am486DX系列數(shù)據(jù)手冊(cè)? 1.87MB(PDF格式)
文件頁(yè)數(shù): 1/66頁(yè)
文件大?。?/td> 1923K
代理商: 20736
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
DISTINCTIVE CHARACTERISTICS
I
High-Performance Design
-
Industry-standard write-back cache support
-
Frequent instructions execute in one clock
-
105.6-million bytes/second burst bus at 33 MHz
-
Flexible write-through and write-back address
control
-
Advanced 0.35-
μ
CMOS-process technology
-
Dynamic bus sizing for 8-, 16-, and 32-bit buses
-
Supports “soft reset” capability
I
High On-Chip Integration
-
16-Kbyte unified code and data cache
-
Floating-point unit
-
Paged, virtual memory management
I
Enhanced System and Power Management
-
Stop clock control for reduced power
consumption
-
Industry-standard two-pin System Management
Interrupt (SMI) for power management indepen-
dent of processor operating mode and operating
system
Static design with Auto Halt power-down support
Wide range of chipsets supporting SMM avail-
able to allow product differentiation
I
Complete 32-Bit Architecture
-
Address and data buses
-
All registers
-
8-, 16-, and 32-bit data types
I
Standard Features
-
3-V core with 5-V tolerant I/O
-
Wide range of chipsets and support available
through the AMD FusionE86
SM
Program
I
168-Pin PGA Package or 208-Pin SQFP Package
I
IEEE 1149.1 JTAG Boundary-Scan Compatibility
-
-
GENERAL DESCRIPTION
The Enhanced Am486
DX Microprocessor Family is an
addition to the AMD E86 family of embedded micropro-
cessors. This new family enhances system performance
by incorporating a 16-Kbyte write-back cache to the ex-
isting flexible clock control and enhanced SMM features
of a 486 CPU.
The Enhanced Am486DX microprocessor family en-
ables write-back configuration through software and
cacheable access control. On-chip cache lines are con-
figurable as either write-through or write-back. The CPU
clock control feature permits the CPU clock to be stopped
under controlled conditions, allowing reduced power
consumption during system inactivity. The SMM function
is implemented with an industry standard two-pin inter-
face.
Since the Enhanced Am486DX microprocessor family is
supported as an embedded product, customers can rely
on continued cost reduction, a long-term supply, and
extended temperature products.
In addition, customers have access to a large selection
of inexpensive development tools, compilers, and
chipsets. A large number of PC operating systems and
Real Time Operating Systems (RTOS) support the En-
hanced Am486DX microprocessor family. This results in
decreased development costs and improved time to mar-
ket.
Table 1 shows available processors in the Enhanced
Am486DX microprocessor family. See page 54 for in-
formation on how these parts differ from other Am486
processors.
Table 1. Clocking Options
Operating
Frequency
Am486DX5-133
Am486DX5-133
Am486DX4-100
Am486DX4-100
Am486DX2-66
Am486DX2-66
Input Clock
Available Package
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
168-pin PGA
208-pin SQFP
PRELIMINARY
Enhanced Am486
DX
Microprocessor Family
Publication #
20736
Rev
: B
Amendment
/0
Issue Date:
March 1997
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