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參數資料
| 型號： | 20726 |
| 英文描述： | 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology |
| 中文描述： | 3DNow?。考夹g手冊的AMD - K6處理器多媒體技術 |
| 文件頁數： | 59/120頁 |
| 文件大?。?/td> | 1284K |
| 代理商： | 20726 |
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MMX Instruction Set
53
20726D/0—January 2000
AMD-K6 MMX Enhanced Processor Multimedia Technology
Preliminary Information
PCMPGTB
mnemonic
opcode
description
PCMPGTB mmreg1, mmreg2/mem64
0F 64h
Compare signed packed 8-bit values for magnitude
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
The PCMPGTB instruction operates on signed 8-bit data values. The instruction
compares two signed 8-bit values to determine if the value in the destination operand
is greater than the corresponding signed 8-bit data value in the source operand.
If the value in the destination operand is greater than the value in the source operand,
all the bits in that 8 bits of the destination operand are set to 1. If the value in the
destination operand is equal to or less than the value in the source operand, all the
bits in that 8 bits of the destination operand are set to 0.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate MMX instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)
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