參數(shù)資料
型號: 20726
英文描述: 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology
中文描述: 3DNow?。考夹g(shù)手冊的AMD - K6處理器多媒體技術(shù)
文件頁數(shù): 116/120頁
文件大?。?/td> 1284K
代理商: 20726
110
MMX Instruction Set
AMD-K6 MMX Enhanced Processor Multimedia Technology
20726D/0—January 2000
Preliminary Information
Functional Illustration of the PUNPCKLWD Instruction
In the following figure, the destination register is shown at the center to illustrate the
flow of data from the two source operands.
In the functional illustration of the PUNPCKLWD instruction, the 16-bit values from
mmreg1 are stored in the low-order 16 bits of the 32-bit result. The 16-bit values from
the mmreg2/mem32 source operand are stored in the high-order 16 bits of the 32-bit
result. This is an example of the use of the PUNPCKLWD instruction to assemble
32-bit operands from the high and low 16-bit results produced by the PMULHW and
PMULLW instructions. In this example, the high and low 16-bit results are interleaved
to produce the signed 32-bit results 06FD_5FCFh and 0000_0001h.
source mmreg2
destination mmreg1
source mmreg1
1569h
06FDh
4030h
0000h
0001h
0001h
06FDh
0000h
5FCFh
F98Ch
5FCFh
7662h
63
63
0
0
0000h
06FDh
0
source mem32
destination mmreg1
source mmreg1
06FDh
0001h
0000h
5FCFh
31
63
31
4030h
0001h
5FCFh
7662h
0
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