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參數(shù)資料
| 型號(hào)： | 20726 |
| 英文描述： | 3DNow!? Technology Manual AMD-K6 Processor Multimedia Technology |
| 中文描述： | 3DNow??？技術(shù)手冊(cè)的AMD - K6處理器多媒體技術(shù) |
| 文件頁數(shù)： | 8/120頁 |
| 文件大小： | 1284K |
| 代理商： | 20726 |
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AMD-K6 Processor Multimedia Technology
AMD-K6 MMX Enhanced Processor Multimedia Technology
20726D/0—January 2000
Preliminary Information
instruction set as its native mode of operation. Only this native
mode enables delivery of maximum performance when running
PC software.
The AMD-K6 processor delivers leading-edge performance to
mainstream PC systems running industry-standard x86
software. The AMD-K6 processor implements advanced design
techniques like instruction pre-decoding, dual x86 opcode
decoding, single-cycle internal RISC operations, parallel
execution units, out-of-order execution, data forwarding,
register renaming, and dynamic branch prediction. In other
words, the AMD-K6 is capable of issuing, executing, and
retiring multiple x86 instructions per cycle, resulting in
superior scaleable performance.
This document describes the multimedia technology of the
AMD-K6 processor, including data types, instructions, and
programming considerations.
Multimedia Technology Architecture
The multimedia technology in the AMD-K6 MMX enhanced
processor is designed to accelerate media and communication
applications. Specialized applications that use music synthesis,
speech synthesis, speech recognition, audio and video
compression and decompression, full motion video, 2D and 3D
graphics, and video conferencing, can take advantage of the
AMD-K6 processor multimedia technology. The multimedia
technology implements new instructions, new data types, and
powerful parallel processing (Single Instruction Multiple Data,
SIMD) techniques that can significantly increase the
performance of these applications.
Key Functionality
At the lowest levels, multimedia applications (audio, video, 3D
graphics, and telephony, etc.) contain many similar functions.
When these functions are performed on a processor that does
not have MMX capability, the processor is heavily burdened by
the computational requirements of this information. Processors
executing the MMX instructions increase the performance of
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