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參數(shù)資料
| 型號： | 24850 |
| 英文描述： | Parasite-Power Digital Thermometer |
| 中文描述： | Socket 754的設計和資格要求 |
| 文件頁數(shù)： | 31/40頁 |
| 文件大小： | 2405K |
| 代理商： | 24850 |
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24850 Rev. 3.07 August 2003
Socket 754 Design and Qualification Requirements
Figure 8. Current/Voltage Definitions and Equivalent Circuit of the Partial “Loop” Inductance
Matrix
7.1.4.1
Test Procedure
As shown in Figure 7 on page 30, the partial inductance matrix of a mated three-pin combination that
is extracted from a mated two-pin loop inductance measurements with one of the pins used as the
reference (current return). Use the formula in Equation (1) below to calculate the Mated Partial Loop
Inductance from measured mated loop inductance data.
2
3
2
1
12
loop
loop
loop
L
L
L
M
+
=
.
(1)
7.1.4.2
Test Condition
Test Frequencies are 500 MHz and 2 GHz.
7.1.4.3
M < 2 nH
±
10%—three pin loop with one pin used as reference.
Measurement of the off diagonal entries in the loop partial inductance matrix.
Diagonal entries of this matrix correspond to Mated Loop Inductance and must meet specified
values in Section 7.1.3.3. on page 30.
Requirements
7.2
Differential Impedance Definition
If the dimensions of the socket pins and the spacing between them are small compared to the
wavelength of the highest frequency component of interest, then the impedance of the three-pin
configuration shown in Figure 6 on page 29 and Figure 8 on page 31 can be calculated approximately
from the lumped “l(fā)oop” inductance and Maxwell capacitance matrices. When pins 1 and 2 in (Figure
8 on page 31) are driven differentially, with pin 3 acting as ground, then the differential impedance of
the transmission line formed by this pin configuration is given by
12
12
2
C
C
M
L
Z
loop
diff
+
=
.
(2)
Chapter 7
Electrical Qualification Requirements
31
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