參數(shù)資料
型號： 24850
英文描述： Parasite-Power Digital Thermometer
中文描述： Socket 754的設(shè)計和資格要求
文件頁數(shù)： 37/40頁
文件大小： 2405K
代理商： 24850
24850 Rev. 3.07 August 2003
Socket 754 Design and Qualification Requirements
Table 3. Summary of Required Measurements for the Socket 754
Measured
Quantity
Mated partial self-
inductance of a
single pin.
This is the only
quantity in the
specification that
need not be
measured.
Definition
Specified
Value(s)
Four nH
maximum
assuming the
current return at
infinity.
Measurement
Applicable
Standard
See, Section 7.1.2,
Mated Partial Self
Inductance on page
29, for the discussion
on the mated self-
partial inductance.
Use a validated
“industry-standard”
3D EM field solver.
This computed
quantity
must not be
used in any
calculations involving
measured data.
Values obtained
from an accurate
detailed 3-D EM
field solver model
are acceptable.
Partial self-
inductance of a
single mated
(interposer-socket
combination) pin
that is calculated
using a 3-D EM
field solver.
This quantity cannot be
measured directly nor
can it be calculated
uniquely from the
measurements.
Mated loop
inductance of two
nearest pins (i.e.,
pins separated by
shortest distance).
The inductance of a
loop formed by two
nearest mated pins.
All current is
injected into one
pin and returned
through the other.
Three nH
±
10%
The inductance of a
loop formed by two
nearest pins, which are
shorted at the bottom of
the socket, with current
injected into one pin
and returned through
the other.
See Section 7.1.3,
Mated Loop
Inductance, on page
30, for specified pin
configurations.
Mated partial
“l(fā)oop” inductance
matrix
L
three neighboring
pins.
partial
loop
of
Partial inductance
matrix of a mated
three-pin
combination
extracted from
mated two-pin
loop- inductance
measurements.
One of the pins is
used as the
reference (current
return).
loop
L
≤
3nH
±
10%
These are the
diagonal entries
in the “l(fā)oop”
partial inductance
matrix.
M
12
< 2
nH
±
10%. These
are the off-
diagonal entries
in the “l(fā)oop”
partial inductance
matrix.
The partial inductance
matrix is extracted from
a series of two-pin loop
inductance
measurements (as
described above) for
specified three-pin
configurations.
See Section7.1.4,
Mated Partial Loop
Inductance on page 30
for the definition of
this matrix and the
measurements that
should be used to
back-calculate the self
and mutual partial
“l(fā)oop” inductances.
Use the formulas in
paragraph 7.1.4,
Mated Partial Loop
Inductance Matrix,
equation (1)provided
in this document.
Chapter 7
Electrical Qualification Requirements
37
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