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參數(shù)資料
| 型號： | 28230-13 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208 |
| 封裝： | PLASTIC, MQFP-208 |
| 文件頁數(shù)： | 182/237頁 |
| 文件大?。?/td> | 3214K |
| 代理商： | 28230-13 |
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36
3.0 Functional Description
3.3 Local Processor Interface
Bt8230
ATM Segmentation and Reassembly Controller—SAR
N8230DS1F
3.3.2 Bus Cycle Descriptions
Throughout the bus cycle descriptions, cycle refers to a single SYSCLK cycle
ending with a rising edge. An arbitration cycle is one in which the memory
requests from the local processor and internal memory consumers are compared,
and the one with the highest priority is granted the memory access on the next
cycle. The priority for the users of local memory is: 1) Reassembly (RSM), 2)
Segmentation (SEG), 3) PCI and 4) Local. A memory access that was previously
arbitrated may occur on an arbitration cycle. Once the local processor has suc-
cessfully acquired the memory controller, it holds the bus until it is relinquished
by the assertion of PBLAST* on the last data cycle. Therefore, local processor
burst transfers will always be completed and may theoretically be of arbitrary
length. However, in practice, burst transfers should be limited to four or less
words. The maximum arbitration delay for a local processor access is on the order
of 20 cycles; however, it will typically be from 1 to 4 cycles. This parameter is
heavily influenced by the SYSCLK frequency, line rate, number of VCCs, idle
cell ratio, and SRAM access speed. Therefore, a system design in which local
processor accesses must occur within a fixed time period is not recommended.
3.3.2.1 Single Read
Cycle, Zero Wait State
Figure 3-10 illustrates a single read cycle with zero wait states. During the
address cycle (cycle 1) at the rising edge of SYSCLK with PCS* and PAS* active,
a memory request is generated by the processor interface circuitry. Also at this
time, the read/write select, bank select, and word select inputs (PWNR,
PBSEL[1,0], and PADDR[1,0]) are internally latched. Note that the byte enables
(PBE[3:0]*) are “don’t cares” during reads. During cycle 2, this local processor
memory request is processed by the memory arbitration circuitry. If no other
memory consumers request an access on the same cycle, the local processor is
granted access on cycle 3. However, to take into account bus transceiver turn-
around, cycle 3 is always a wait or bus recovery state which gives sufficient time
for the address from the processor to access the SRAM. For zero wait state
SRAM, unless a wait state is inserted by the processor, the data is available to be
latched into the processor on cycle 4, which is indicated by the assertion of
PRDY*. Cycle 5 is an arbitration cycle for the internal memory consumers which
may have requested access during the processor access. It also serves as a bus
PRDY*
O
Processor interface ready signal—A logic low on this signal at rising edge of SYSCLK indicates that
the present cycle has been completed. If a read cycle, the data is valid to latch by the processor; if a
write cycle, the data has been written and may be removed from the bus. When PRDY* is active,
wait states may be inserted with PWAIT*, or a single or burst cycle may be terminated by
PBLAST*2.
PDAEN*
O
Processor data and address bus enable—Connects to output enable input of bidirectional trans-
ceiver and buffer to enable data and address for processor cycles. May also be used to indicate that
the processor has successfully arbitrated for access to the memory controller3.
1Direction given with respect to the Bt8230.
2This output corresponds to the READY* or RDYRCV* input in the i960 architecture.
3The processor system is responsible for controlling the direction of the bidirectional data bus transceiver. In the i960 architec-
ture, this may be controlled by the DT/R* signal.
Table 3-2. Processor Interface Pins (2 of 2)
Signal
Dir1
Description
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