參數(shù)資料
型號(hào): 28230-13
廠商: CONEXANT SYSTEMS
元件分類: 數(shù)字傳輸電路
英文描述: ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208
封裝: PLASTIC, MQFP-208
文件頁(yè)數(shù): 224/237頁(yè)
文件大小: 3214K
代理商: 28230-13
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74
3.0 Functional Description
3.5 Reassembly Coprocessor
Bt8230
ATM Segmentation and Reassembly Controller—SAR
N8230DS1F
3.5.2 Hashing
The Bt8230 implements a hash algorithm to locate the appropriate RSM VCC
table entry for incoming ATM cells. During reassembly, the Bt8230 looks at the
header of each incoming ATM cell to determine the connection (VCC) to which
the cell belongs. This information is then used to establish where in the host
memory the current reassembly buffer for this connection resides. The pointer to
that buffer location (CBUFF_ADDR) is one of the fields in the reassembly VCC
table entry for that connection. Because ATM cells will be received in an
unknown order from the line, the Bt8230 must manage several incoming data
streams and determine the VCC to which each cell belongs.
3.5.2.1 Hashing
Algorithm
The Bt8230 hashing algorithm passes the 24-bit VPI/VCI pair received from the
line through a truncating function. The hardware hashing function computes the
hash table index as follows:
({VPI[7:0],VCI[15:12]} ^ VCI[11:0]) & (2
TAB_SIZE–1)
Bits 0 through 7 of the VPI are concatenated with bits 12 through 15 of the
VCI to form a 12-bit field. This field is then exclusive-ORed with bits 0 through
11 of the VCI. The result is masked with a bitmask generated from the
TAB_SIZE field of the Reassembly Control Register [RSM_CTRL; 0x70]. This
function shortens the identifier to an N-bit field, where N is between 0 and 14.
The Bt8230 then multiplies the N-bit offset by four and adds the result to the con-
tents of the Reassembly Hash Table Base Register [RSM_HBASE; 0x7C] to pro-
duce the actual address of a pointer to a hash bucket chain. When TAB_SIZE is
equal to 14, a special 14-bit hash index function is enabled. The hash table index
is calculated as follows:
({VPI[7:0],VCI[15:14],’0000’} ^ VCI[13:0])
The hash bucket chain is processed sequentially for a hash bucket match. The
hash bucket index comparator computes the logical-AND of the 32-bit MASK
field of a hash bucket read from memory with the 32-bit ATM header and com-
pares the result with the 32-bit HEADER field in the same hash bucket to gener-
ate a match signal. The match signal is used by the reassembly coprocessor to
determine whether the required hash bucket has been found. If a match is
obtained, the current hash bucket is used to process the cell; otherwise, the reas-
sembly coprocessor reads a pointer to the next sequential bucket in the list from
the NEXT field and repeats the matching process. If NEXT contains a null (zero)
pointer, the end of the list is assumed to have been reached; the matching is then
declared unsuccessful, the cell is discarded, and the VPI_VCI_ERR counter at the
top of the hash table is incremented.
NOTE:
A bit bucket can be set up for cells with unknown VPI/VCIs. Instead of a
NULL NEXT pointer in the last hash bucket, a common connection can be
set up to handle these cells. By setting the AAL_TYPE to AAL0, a status
entry will be written for every cell with unknown VPI/VCI and the cell
will be written to a cell buffer.
Once a hash bucket match occurs, the VCC_PNTR is used to access the
RSM_VCC_TABLE. For AAL3/4, the pointer to the VCC table (VCC_PNTR) is
found from the result of the following calculation:
hash_bucket_base_address + 4 + (MID & (2
MID_BITS –1))
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