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參數(shù)資料
| 型號： | 28F008SC |
| 廠商： | Intel Corp. |
| 英文描述： | 8-MBIT SmartVoltage FlashFile Memory(8M位智能電壓閃速存儲器) |
| 中文描述： | 8兆SmartVoltage FlashFile內(nèi)存（800萬位智能電壓閃速存儲器） |
| 文件頁數(shù)： | 20/42頁 |
| 文件大小： | 725K |
| 代理商： | 28F008SC |
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BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
E
20
PRELIMINARY
4.10
Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
HH
on the RP# pin. See Table 6 for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is initiated using a
two-cycle command sequence. A clear block
lock-bits setup is written first. Then, the device
automatically outputs status register data when
read (see Figure 12). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# pin output or status register
bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to
“1.” Also, a
reliable clear block lock-bits operation can only
occur when V
CC
= V
CC2/3
and V
PP
= V
PPH1/2/3
. If a
clear block lock-bits operation is attempted while
V
PP
≤
V
PPLK
, SR.3 and SR.5 will be set to “1.” In the
absence of this high voltage, the block lock-bits
content are protected against alteration. A suc-
cessful clear block lock-bits operation requires that
the master lock-bit is not set or, if the master lock-
bit is set, that RP# = V
HH
. If it is attempted with the
master lock-bit set and RP# = V
IH
, SR.1 and SR.5
will be set to “1” and the operation will fail. A clear
block lock-bits operation with V
IH
< RP# < V
HH
produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
V
PP
or V
CC
transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
Table 6. Write Protection Alternatives
Operation
Master
Lock-Bit
Block
Lock-Bit
RP#
Effect
Block Erase or
0
V
IH
or V
HH
V
IH
V
HH
Block Erase and Program Enabled
Program
X
1
Block is Locked. Block Erase and Program Disabled
Block Lock-Bit Override. Block Erase and Program
Enabled
Set Block
0
X
V
IH
or V
HH
V
IH
V
HH
Set Block Lock-Bit Enabled
Lock-Bit
1
X
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
Master Lock-Bit Override. Set Block Lock-Bit
Enabled
Set Master
X
X
V
IH
V
HH
Set Master Lock-Bit Disabled
Lock-Bit
Set Master Lock-Bit Enabled
Clear Block
0
X
V
IH
or V
HH
V
IH
Clear Block Lock-Bits Enabled
Lock-Bits
1
X
Master Lock-Bit is Set. Clear Block Lock-Bits
Disabled
V
HH
Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
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