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參數(shù)資料
| 型號： | 28F008SC |
| 廠商： | Intel Corp. |
| 英文描述： | 8-MBIT SmartVoltage FlashFile Memory(8M位智能電壓閃速存儲器) |
| 中文描述： | 8兆SmartVoltage FlashFile內(nèi)存（800萬位智能電壓閃速存儲器） |
| 文件頁數(shù)： | 26/42頁 |
| 文件大小： | 725K |
| 代理商： | 28F008SC |
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BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
E
26
PRELIMINARY
SR.7 =
0
1
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
1
0
Read Status Register
Data (See Above)
1
0
Read Status
Register
V Range Error
1
0
Command Sequence
Error
SR.3 =
SR.4 =
SR.4,5 =
Set Lock-Bit Error
Bus
Operation
Command
Comments
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Check SR.4
1 = Set Lock-Bit Reset Error
Standby
Bus
Operation
Command
Comments
Write
Write
Set
Block/Master
Lock-Bit Setup
Read
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Status Register Data
Standby
Set
Block or Master
Lock-Bit Confirm
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Set Lock-Bit Successful
Standby
0
1
Device Protect Error
SR.1 =
Check SR.3
1 = V Error Detect
Check SR.1
1 = Device Protect Detect
RP# = V ,
(Set Master Lock-Bit Operation)
RP# = V , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
Figure 11. Set Block and Master Lock-Bit Flowchart
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