參數(shù)資料
型號： 28F008SC
廠商： Intel Corp.
英文描述： 8-MBIT SmartVoltage FlashFile Memory(8M位智能電壓閃速存儲器)
中文描述： 8兆SmartVoltage FlashFile內(nèi)存（800萬位智能電壓閃速存儲器）
文件頁數(shù)： 33/42頁
文件大小： 725K
代理商： 28F008SC
E
BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY
33
PRELIMINARY
TEST POINTS
INPUT
OUTPUT
1.35
2.7
0.0
1.35
AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35
V. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for V
CC
= 2.7 V
3.6 V
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V
CC
= 3.3 V ± 0.3 V and V
CC
= 5.0 V ± 5%
(High Speed Testing Configuration)
TEST POINTS
INPUT
OUTPUT
2.0
0.8
0.8
2.0
2.4
0.45
AC test inputs are driven at V
(2.4 V
) for a Logic "1" and V
(0.45 V
) for a Logic "0." Input timing begins at V
IH
(2.0 V
TTL
) and V
IL
(0.8 V
TTL
). Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for V
CC
= 5.0 V
±
10%
(Standard Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
R
L
C
L
OUT
= 3.3 K
NOTE:
C
L
includes Jig Capacitance
Figure 16. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CC
= 3.3 V
±
0.3 V, 2.7 V
3.6 V
50
V
CC
= 5 V
±
5%
30
V
CC
= 5 V
±
10%
100
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