參數(shù)資料
型號(hào)： 28F010
廠商： Intel Corp.
英文描述： 1024K (128K x 8) CMOS FLASH MEMORY
中文描述： 1024K（128K的× 8）的CMOS閃存
文件頁(yè)數(shù)： 10/30頁(yè)
文件大小： 405K
代理商： 28F010
28F010
Program-Verify Command
The 28F010 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at ran-
dom. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the ris-
ing edge of its WE
Y
pulse. The program-verify oper-
ation stages the device for verification of the byte
last programmed. No new address information is
latched.
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F010 Quick Pulse Programming algorithm, il-
lustrates how commands are combined with bus op-
erations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some sup-
pliers have implemented redundancy schemes, re-
ducing cycling failures to insignificant levels. Howev-
er, redundancy requires that cell size be doubledD
an expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting im-
provements in cycling reliability come without in-
creasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carry-
ing ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probabili-
ty of oxide defects in the region. Finally, the peak
electric
field
during
erasure
is
approximately
2 MV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure.
The 28F010 is capable or 100,000 program/erase
cycles. The device is programmed and erased using
Intel’s Quick Pulse Programming and Quick Erase
algorithms. Intel’s algorithmic approach uses a se-
ries of operations (pulses), along with byte verifica-
tion, to completely and reliably erase and program
the device.
For further information, see Reliability Report RR-60.
QUICK PULSE PROGRAMMING ALGORITHM
The Quick Pulse Programming algorithm uses pro-
gramming operations of 10
m
s duration. Each opera-
tion is followed by a byte verification to determine
when the addressed byte has been successfully pro-
grammed. The algorithm allows for up to 25 pro-
gramming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with V
PP
at high voltage. Figure 5 illus-
trates the Quick Pulse Programming algorithm.
QUICK ERASE ALGORITHM
Intel’s Quick Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algo-
rithm employs a closed-loop flow, similar to the
Quick Pulse Programming algorithm, to simulta-
neously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory.
Reading FFH data from the device would immedi-
ately be followed by device programming.
For devices being erased and reprogrammed, uni-
form and reliable erasure is ensured by first pro-
gramming all bits in the device to their charged state
(Data
e
00H). This is accomplished, using the Quick
Pulse Programming algorithm, in approximately two
seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data
e
FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is en-
countered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored ad-
dress location. Erasure typically occurs in one sec-
ond. Figure 6 illustrates the Quick Erase algorithm.
10
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