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參數(shù)資料
| 型號： | 28F010 |
| 廠商： | Intel Corp. |
| 英文描述： | 1024K (128K x 8) CMOS FLASH MEMORY |
| 中文描述： | 1024K（128K的× 8）的CMOS閃存 |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 405K |
| 代理商： | 28F010 |
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28F010
290207–1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
A
0
–A
16
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a write cycle.
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUT/OUTPUT:
Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
CE
Y
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE
Y
is active low; CE
Y
high
deselects the memory device and reduces power consumption to
standby levels.
OE
Y
INPUT
OUTPUT ENABLE:
Gates the devices output through the data buffers
during a read cycle. OE
Y
is active low.
WE
Y
INPUT
WRITE ENABLE:
Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE
Y
pulse.
Note:
With V
PP
s
6.5V, memory contents cannot be altered.
V
PP
ERASE/PROGRAM POWER SUPPLY
for writing the command
register, erasing the entire array, or programming bytes in the array.
V
CC
DEVICE POWER SUPPLY
(5V
g
10%)
V
SS
GROUND
NC
NO INTERNAL CONNECTION
to device. Pin may be driven or left
floating.
2
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F0101024K | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| 28F010120EI | 制造商:Advanced Micro Devices 功能描述: |
| 28F010-120EI | 制造商:undefined 功能描述: |
| 28F010120JC | 制造商: 功能描述: 制造商:Advanced Micro Devices 功能描述: 制造商:undefined 功能描述: |
| 28F010-120JC | 制造商:undefined 功能描述: |
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