Intel
82801BA ICH2 Datasheet
5-129
Functional Description
NOTE:
The external microcontroller is responsible to make sure that it does not update the contents of the data
byte registers until they have been read by the system processor. The ICH2 overwrites the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH2 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
Table 5-85. Slave Write Registers
Register
Function
0
Command Register. See Table 65 below for legal values written to this register.
1–3
Reserved
4
Data Message Byte 0
5
Data Message Byte 1
6–7
Reserved
8
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.
9–FFh
Reserved
Table 5-86. Command Types
Command
Type
Description
0
Reserved
1
WAKE/SMI#:
Wake system if it is not already awake. If the system is already awake, an
SMI# is generated.
2
Unconditional Powerdown:
This command sets the PWRBTNOR_STS bit and has the
same effect as the Powerbutton Override occurring. This functionality depends upon the
BIOS having cleared the PWRBTN_STS bit.
3
Hard Reset without Cycling:
This causes a hard reset of the system (does not include
cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1
set to 1, but bit 3 set to 0.
4
Hard Reset System:
This causes a hard reset of the system (including cycling of the power
supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
5
Disable the TCO Messages.
This command disables the ICH2 from sending Heartbeat and
Event messages (as described in
Section 5.13.2
). Once this command has been executed,
Heartbeat and Event message reporting can only be re-enabled by assertion and
deassertion of the RSMRST# signal.
6
WD RELOAD:
Reload watchdog timer.
7–FFh
Reserved
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