Intel
82801BA ICH2 Datasheet
6-1
Register and Memory Mapping
Register and Memory Mapping
6
The ICH2 contains registers that are located in the processor’s I/O space and memory space and
sets of PCI configuration registers that are located in PCI configuration space. This chapter
describes the ICH2 I/O and memory maps at the register-set level. Register access is also
described. Register-level address maps and Individual register bit descriptions are provided in the
following chapters. The following notations and definitions are used in the register/instruction
description chapters.
RO
Read Only. In some cases, If a register is read only, writes to this register
location have no effect. However, in other cases, two separate registers
are located at the same location where a read accesses one of the registers
and a write accesses the other register. See the I/O and memory map
tables for details.
WO
Write Only. In some cases, If a register is write only, reads to this register
location have no effect. However, in other cases, two separate registers
are located at the same location where a read accesses one of the registers
and a write accesses the other register. See the I/O and memory map
tables for details.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and
written. However, a write of 1 clears (sets to 0) the corresponding bit and
a write of 0 has no effect.
Default
When ICH2 is reset, it sets its registers to predetermined default states.
The default state represents the minimum functionality feature set
required to successfully bring up the system. Hence, it does not represent
the optimal system configuration. It is the responsibility of the system
initialization software to determine configuration, operating parameters,
and optional system features that are applicable, and to program the
ICH2 registers accordingly.
Bold
Register bits that are highlighted in bold text indicate that the bit is
implemented in the ICH2. Register bits that are not implemented or are
rewired will remain in plain text.
6.1
PCI Devices and Functions
The ICH2 incorporates a variety of PCI functions as shown in
Table 6-1
. These functions are
divided into three logical devices (B0:D30, B0:D31 and B1:D8). D30 is the hub interface-to-PCI
bridge, D31 contains the PCI-to-LPC Bridge, IDE Controller, USB Controllers, SMBus Controller
and the AC’97 Audio and Model Controller functions. B1:D8 is the integrated LAN Controller.
Note:
From a software perspective, the integrated LAN Controller resides on the ICH2’s external PCI bus
(See
Section 5.1.2
). This is typically Bus 1, but may be assigned a different number depending on
system configuration.
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