LAN Controller Registers (B1:D8:F0)
7-2
Intel
82801BA ICH2 Datasheet
7.1.1
VID—Vendor ID Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
00–01h
8086h
Attribute:
Size:
RO
16 bits
7.1.2
DID—Device ID Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
02–03h
2449h
Attribute:
Size:
RO
16 bits
7.1.3
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
04–05h
0000h
Attribute:
Size:
RO, R/W
16 bits
Bit
Description
15:0
Vendor Identification Number.
This is a 16-bit value assigned to Intel.
Bit
Description
15:0
Device Identification Number.
This is a 16 bit value assigned to the ICH2 integrated LAN
Controller.
Bit
Description
15:10
Reserved.
9
Fast Back to Back Enable (FBE
)
—RO. Hardwired to 0. The integrated LAN Controller will not run
fast back-to-back PCI cycles.
8
SERR# Enable (SERR_EN)—
R/W.
1 = Enable. Allow SERR# to be generated.
0 = Disable.
Wait Cycle Control (WCC)—RO. Hardwired to 0. Not implemented.
6
Parity Error Response (PER)
—R/W
1 = The integrated LAN Controller will take normal action when a PCI parity error is detected. The
generation of parity is also enabled on the hub interface.
0 = The LAN Controller will ignore PCI parity errors.
5
VGA Palette Snoop (VPS)—RO. Hardwired to 0. Not Implemented.
4
Memory Write and Invalidate Enable (MWIE)
—R/W.
0 = Disable. The LAN Controller will not use the Memory Write and Invalidate command.
1 = Enable.
3
Special Cycle Enable (SCE)—RO. Hardwired to 0. The LAN Controller ignores special cycles.
2
Bus Master Enable (BME)
—R/W.
1 = Enable. The ICH2’s integrated may function as a PCI bus master.
0 = Disable.
1
Memory Space Enable (MSE)
—R/W.
1 = Enable. The ICH2’s integrated LAN Controller will respond to the memory space accesses.
0 = Disable.
0
I/O Space Enable (IOE)
—R/W.
1 = Enable. The ICH2’s integrated LAN Controller will respond to the I/O space accesses.
0 = Disable.
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