參數(shù)資料
型號(hào): AD9271BSVZRL-50
廠商: Analog Devices Inc
文件頁數(shù): 14/60頁
文件大?。?/td> 0K
描述: IC ADC OCT 12BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 1.49W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)差分,單極
AD9271
Rev. B | Page 21 of
60
LNA
LI-x
LG-x
LO-x
DOUTx+
DOUTx–
CS
T/R
SWITCH
CLG
CFB
RFB2
CSH
GAIN
INTERPOLATOR
LOSW-x
RFB1
TO
SWITCH
ARRAY
gm
CDWx+
CDWx–
ATTENUATOR
–30dB TO 0dB
12-BIT
PIPELINE
ADC
SERIAL
LVDS
+24dB
GA
IN
0
630
4-
0
71
AAF
GA
IN
+
AD9271
T
R
ANS
D
UCE
R
Figure 40. Simplified Block Diagram of a Single Channel
CHANNEL OVERVIEW
Each channel contains both a TGC signal path and a CW Doppler
signal path. Common to both signal paths, the LNA provides user-
adjustable input impedance termination. The CW Doppler path
includes a transconductance amplifier and a crosspoint switch. The
TGC path includes a differential X-AMP VGA, an antialiasing
filter, and an ADC. Figure 40 shows a simplified block diagram
with external components.
The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the
LNA is designed to be driven from a single-ended signal source.
Low Noise Amplifier (LNA)
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input impedance matching.
A simplified schematic of the LNA is shown in Figure 41. LI-x is
capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of around 1.4 V and centers
the output common-mode levels at 0.9 V (VDD/2). A capacitor,
CLG, of the same value as the input coupling capacitor, CS, is
connected from the LG-x pin to ground.
LI-x
CS
CLG
CFB
CSH
LG-x
LO-x
LOSW-x
VCM
VO+
VO–
RFB1
RFB2
06
304-
10
1
T/R
SWITCH
T
R
A
N
SD
UC
ER
AVDD2
Figure 41. Simplified LNA Schematic
The LNA supports differential output voltages as high as 2 V p-p
with positive and negative excursions of ±0.5 V from a common-
mode voltage of 0.9 V. The LNA differential gain sets the maximum
input signal before saturation. One of three gains is set through
the SPI. The corresponding input full scale for the gain settings
of 5, 6, or 8 is 400 mV p-p, 333 mV p-p, and 250 mV p-p,
respectively. Overload protection ensures quick recovery time
from large input voltages. Because the inputs are capacitively
coupled to a bias voltage near midsupply, very large inputs can
be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
noise voltage of 1.2 nV/√Hz. This is achieved with a current
consumption of only 16 mA per channel (30 mW). On-chip
resistor matching results in precise single-ended gains, which
are critical for accurate impedance control. The use of a fully
differential topology and negative feedback minimizes distortion.
Low HD2 is particularly important in second-harmonic ultrasound
imaging applications. Differential signaling enables smaller swings
at each output, further reducing third-order distortion.
Active Impedance Matching
The LNA consists of a single-ended voltage gain amplifier with
differential outputs and the negative output externally available.
For example, with a fixed gain of 6× (15.6 dB), an active input
termination is synthesized by connecting a feedback resistor
between the negative output pin, LO-x, and the positive input
pin, LI-x. This technique is well known and results in the input
resistance shown in Equation 1:
)
2
1
(
A
R
FB
IN
+
=
(1)
where A/2 is the single-ended gain or the gain from the LI-x
inputs to the LO-x outputs.
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