參數(shù)資料
型號： AD9271BSVZRL-50
廠商： Analog Devices Inc
文件頁數(shù)： 29/60頁
文件大?。?/td> 0K
描述： IC ADC OCT 12BIT 50MSPS 100-TQFP
標準包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 50M
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 8
功率耗散（最大）： 1.49W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應商設備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，單極；8 個差分，單極
AD9271
Rev. B | Page 35 of
60
SERIAL PORT INTERFACE (SPI)
The AD9271 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. This offers
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the Analog Devices, Inc., AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Three pins define the serial port interface, or SPI: the SCLK,
SDIO, and CSB pins. The SCLK (serial clock) is used to
synchronize the read and write data presented to the device.
The SDIO (serial data input/output) is a dual-purpose pin that
allows data to be sent to and read from the device’s internal
memory map registers. The CSB (chip select bar) is an active
low control that enables or disables the read and write cycles
(see Table 13).
Table 13. Serial Port Pins
Pin
Function
SCLK
Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.
CSB
Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 71 and Table 14.
In normal operation, CSB is used to signal to the device that SPI
commands are to be received and processed. When CSB is brought
low, the device processes SCLK and SDIO to process instructions.
Normally, CSB remains low until the communication cycle is
complete. However, if connected to a slow device, CSB can be
brought high between bytes, allowing older microcontrollers
enough time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0 and
W1 are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until the CSB is taken
high to end the communication cycle. This allows complete
memory transfers without having to provide additional instruct-
tions. Regardless of the mode, if CSB is taken high in the middle
of any byte transfer, the SPI state machine is reset and the device
waits for a new instruction.
In addition to the operation modes, the SPI port can be configured
to operate in different manners. For example, CSB can be tied
low to enable 2-wire mode. When CSB is tied low, SCLK and
SDIO are the only pins required for communication. Although
the device is synchronized during power-up, caution must be
exercised when using this mode to ensure that the serial port
remains synchronized with the CSB line. When operating in
2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer
be used exclusively. Without an active CSB line, streaming mode
can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the user’s programming device and the serial port of
the AD9271. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
In cases where multiple SDIO pins share a common connection,
care should be taken to ensure that proper VOH levels are met.
Figure 70 shows the number of SDIO pins that can be connected
together, assuming the same load as the AD9271 and the
resulting VOH level.
06
30
4-
1
13
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V
)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
030
20
10
40
50
60
70
80
90
100
Figure 70. SDIO Pin Loading
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