參數(shù)資料
型號(hào)： AD9271BSVZRL-50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/60頁(yè)
文件大小： 0K
描述： IC ADC OCT 12BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 50M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 1.49W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)差分，單極
AD9271
Rev. B | Page 30 of
60
06
30
4-
CH1 500mV/DIV
CH2 500mV/DIV
CH3 500mV/DIV
5.0ns/DIV
Digital Outputs and Timing
The AD9271 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option similar to the IEEE 1596.3 standard by using
the SDIO pin or via the SPI. This LVDS standard can further
reduce the overall power dissipation of the device by approximately
36 mW. See the SDIO Pin section or Table 15 for more
information.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω differ-
ential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9271 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO, DCO, and data stream with
proper trace length and position can be found in Figure 62.
03
4
Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths of less than 24 inches on regular FR-4 material
is shown in Figure 63. Figure 64 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and therefore increase the current) of all
eight outputs in order to drive longer trace lengths (see Figure 65).
Even though this produces sharper rise and fall times on the
data edges, is less prone to bit errors, and improves frequency
distribution (see Figure 65), the power dissipation of the DRVDD
supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, first set the
appropriate bit in Register 0x05. Note that this feature cannot
be used with Bit 4 and Bit 5 in Register 0x15 because these bits
take precedence over this feature. See the Memory Map section
for more details.
06
30
4-
0
35
600
400
–200
200
–100
100
–400
–600
0
–1.5ns
–0.5ns
–1.0ns
0ns
0.5ns
1.0ns
1.5ns
E
Y
E
DI
AG
RAM
V
O
L
T
AG
E
(V
)
EYE: ALL BITS
ULS: 2398/2398
25
0
5
10
15
20
–200ps
–100ps
0ps
100ps
200ps
TIE
J
ITT
E
R
H
IS
T
OG
R
A
M
(
H
it
s
)
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4
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