參數(shù)資料
型號: AD9271BSVZRL-50
廠商: Analog Devices Inc
文件頁數(shù): 59/60頁
文件大?。?/td> 0K
描述: IC ADC OCT 12BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 1.49W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個差分,單極
AD9271
Rev. B | Page 8 of
60
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = 0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK2
Maximum Clock Rate
Full
50
MSPS
Minimum Clock Rate
Full
10
MSPS
Clock Pulse Width High (tEH)
Full
10.0
ns
Clock Pulse Width Low (tEL)
Full
10.0
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
1.5
2.3
3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
1.5
2.3
3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO +
(tSAMPLE/24)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/24) 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data-to-Data Skew (tDATA-MAX tDATA-MIN)
Full
±50
±200
ps
Wake-Up Time (Standby), VGAIN = 0.5 V
25°C
1
μs
Wake-Up Time (Power-Down)
25°C
1
ms
Pipeline Latency
Full
8
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
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