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參數(shù)資料
| 型號： | AD9271BSVZRL-50 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC OCT 12BIT 50MSPS 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 1.49W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個差分，單極 |
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AD9271
Rev. B | Page 37 of
60
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: the
chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x04,
Address 0x05, and Address 0xFF), and the ADC functions
register map (Address 0x08 to Address 0x2D).
The leftmost column of the memory map indicates the register
address number; the default value is shown in the second
rightmost column. The Bit 7 (MSB) column is the start of the
default hexadecimal value given. For example, Address 0x09, the
clock register, has a default value of 0x01, meaning that Bit 7 =
0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the
duty cycle stabilizer in the on condition. By writing 0 to Bit 0 of
this address followed by writing 0x01 in Register 0xFF (transfer
bit), the duty cycle stabilizer turns off. It is important to follow
each writing sequence with a transfer bit to update the SPI
registers. All registers, except Register 0x00, Register 0x02,
Register 0x04, Register 0x05, and Register 0xFF, are buffered with
a master-slave latch and require writing to the transfer bit. For
more information on this and other functions, consult the AN-
877 Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have 0 written into their registers during power-up.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 15, where an
X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
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| AD9271BSVZRL7-25 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
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| AD9272 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal LNA/VGA/AAF/ADC and Crosspoint Switch |
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