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參數(shù)資料
| 型號： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/104頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9558
Data Sheet
Rev. B | Page 18 of 104
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
13
AA
OUT4
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended
1.8 V CMOS.
14
OUT4
O
HSTL, LVDS,
or 1.8 V CMOS
Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
15
AA
OUT3
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 3. This output can be configured as HSTL, LVDS,
or single-ended 1.8 V CMOS.
16
OUT3
O
HSTL, LVDS, or
1.8 V CMOS
Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
18
AA
OUT2
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 2. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
19
OUT2
O
HSTL, LVDS, or
1.8 V CMOS
Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
20
AA
OUT1
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 1. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
21
OUT1
O
HSTL, LVDS,
or 1.8 V CMOS
Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
23
AA
OUT5
EE
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended
1.8 V or 3.3 V CMOS.
24
OUT5
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V
CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-
equivalent termination as described in the Input/Output Termination
Recommendations section.
25, 26
AVDD3
I
Power
3.3 V Analog (Output Driver) Power Supply.
27
AA
OUT0
EE
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Complementary Output 0. This output can be configured as HSTL, LVDS, or single-
ended 1.8 V or 3.3 V CMOS.
28
OUT0
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V
CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-
equivalent termination as described in the Input/Output Termination
Recommendations section.
31
AVDD3
I
Power
3.3V Analog (VCO 2) Power Supply.
32
LDO_VCO2
I
LDO bypass
Output PLL Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin
to ground. This pin is also the ac ground reference for the integrated output PLL
external loop filter.
33
LF_VCO2
I/O
Loop filter
Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this
pin to Pin 32 (LDO_VCO2).
34
NC
No Connect. There is no internal connection for this pin.
35
AVDD
I
Power
1.8 V Analog (APLL) Power Supply.
36
NC
No Connect. There is no internal connection for this pin.
37, 38
AVDD
I
Power
1.8 V Analog (DCO and TDC) Power Supplies.
39
AA
RESET
EE
I
3.3 V CMOS
Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has
an internal 50 k pull-up resistor.
40
PINCONTROL
I
3.3 V CMOS
Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin
programming of the AD9558 configuration during startup. If this pin is low during
startup, the user must program the part via the serial port, or use values that are
stored in the EEPROM.
41
M7
I/O
3.3 V CMOS
Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through
the AD9558 register space.
42
AA
SYNC
EE
I
3.3 V CMOS
Clock Distribution Synchronization Pin. When this pin is activated, output drivers are
held static and then synchronized on a low-to-high transition of this pin. This pin is
used to arm the frame sync function when frame sync mode is enabled and has an
internal 60 k pull-up resistor.
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| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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