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參數(shù)資料
| 型號(hào)： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Data Sheet
AD9558
Rev. B | Page 81 of 104
OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)
Table 67. Clock Distribution Output Synchronization Settings
Address
Bits
Bit Name
Description
0x0500
7
Mask Channel 3 sync
Masks the synchronous reset to the Channel 3 (M3) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 3 from the static SYNC state,
thus allowing the Channel 3 divider to toggle. Channel 3 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
6
Mask Channel 2 sync
Masks the synchronous reset to the Channel 2 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 2 from the static SYNC state,
thus allowing the Channel 2 divider to toggle. Channel 2 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
5
Mask Channel 1 sync
Masks the synchronous reset to the Channel 1 (M2) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 1 from the static SYNC state,
thus allowing the Channel 1 divider to toggle. Channel 1 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this
channel. In addition, the output distribution sync also depends on the setting of Register
0x0405[3].
4
Mask Channel 0 sync
Masks the synchronous reset to the Channel 0 (M0) divider.
0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.
1 = masked. Setting this bit asynchronously releases Channel 0 from the static SYNC state,
thus allowing the Channel 0 divider to toggle. Channel 0 ignores all SYNC events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel. In
addition, the output distribution sync also depends on the setting of Register 0x0405[3].
3
Reserved
Default: 0b.
2
Sync source selection
Selects the sync source for the clock distribution output channels.
0 (default) = direct. The sync pulse happens on the next I/O update.
1 = active reference.
Note that the output distribution sync also depends on the APLL being calibrated and
locked unless Register 0x0405[3] = 1b.
[1:0]
Automatic sync mode
Autosync mode.
00 = disabled. A sync command must be issued manually, or by using the mask sync bits
in this register (Bits[7:4]).
01 = sync on DPLL frequency lock.
10 (default) = sync on DPLL phase lock.
11 = reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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