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參數(shù)資料
| 型號： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Data Sheet
AD9558
Rev. B | Page 33 of 104
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
detector via the profile registers.
The phase lock detector behaves in a manner analogous to
water in a tub (see Figure 38). The total capacity of the tub is
4096 units with 2048 denoting empty, 0 denoting the 50%
point, and +2048 denoting full. The tub also has a safeguard to
prevent overflow. Furthermore, the tub has a low water mark at
1024 and a high water mark at +1024. To change the water
level, the user adds water with a fill bucket or removes water
with a drain bucket. The user specifies the size of the fill and
drain buckets via the 8-bit fill rate and drain rate values in the
profile registers.
0
2048
–2048
1024
–1024
LOCK LEVEL
UNLOCK LEVEL
LOCKED
UNLOCKED
PREVIOUS
STATE
FILL
RATE
DRAIN
RATE
09758-
017
Figure 38. Lock Detector Diagram
The water level in the tub is what the lock detector uses to
determine the lock and unlock conditions. When the water level
is below the low water mark (1024), the detector indicates an
unlock condition. Conversely, when the water level is above the
high water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector simply
holds its last condition. This concept appears graphically in
Figure 38, with an overlay of an example of the instantaneous
water level (vertical) vs. time (horizontal) and the resulting
lock/unlock states.
During any given PFD cycle, the detector either adds water with
the fill bucket or removes water with the drain bucket (one or
the other but not both). The decision of whether to add or
remove water depends on the threshold level specified by the
user. The phase lock threshold value is a 16-bit number stored
in the profile registers and is expressed in picoseconds (ps).
Thus, the phase lock threshold extends from 0 ns to ±65.535 ns
and represents the magnitude of the phase error at the output of
the PFD.
The phase lock detector compares each phase error sample at
the output of the PFD to the programmed phase threshold value.
If the absolute value of the phase error sample is less than or
equal to the programmed phase threshold value, the detector
control logic dumps one fill bucket into the tub. Otherwise,
it removes one drain bucket from the tub. Note that it is not the
polarity of the phase error sample, but its magnitude relative to
the phase threshold value, that determines whether to fill or drain.
If more filling is taking place than draining, the water level in
the tub eventually rises above the high water mark (+1024), which
causes the phase lock detector to indicate lock. If more draining
is taking place than filling, then the water level in the tub eventually
falls below the low water mark (1024), which causes the phase
lock detector to indicate unlock. The ability to specify the threshold
level, fill rate, and drain rate enables the user to tailor the operation
of the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
Note that when the AD9558 enters the free run or holdover
mode, the DPLL phase lock detector indicates an unlocked
state. However, when the AD9558 performs a reference switch,
the lock detector state prior to the switch is preserved during
the transition period.
DPLL Frequency Lock Detector
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds (ps). Thus, the frequency
threshold value extends from 0 μs to ±16.777215 μs. It represents
the magnitude of the difference in period between the reference
and feedback signals at the input to the DPLL. For example, if
the reference signal is 1.25 MHz and the feedback signal is
1.38 MHz, the period difference is approximately 75.36 ns
(|1/1,250,000 1/1,380,000| ≈ 75.36 ns).
Frequency Clamp
The AD9558 DPLL features a digital tuning word clamp that
ensures that the DPLL output frequency stays within a defined
range. This feature is very useful to eliminate undesirable
behavior in cases where the reference input clocks may be
unpredictable. The tuning word clamp is also useful to
guarantee that the APLL never loses lock by ensuring that the
APLL VCO frequency stays within its tuning range.
Frequency Tuning Word History
The AD9558 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user-specified interval. This average tuning word is
used during holdover mode to maintain the average frequency
when no input references are present.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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