- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9673 > AD9558BCPZ (Analog Devices Inc)IC CLOCK TRANSLATOR 64LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/104頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
Data Sheet
AD9558
Rev. B | Page 35 of 104
SYSTEM CLOCK (SYSCLK)
SYSTEM CLOCK INPUTS
Functional Description
The SYSCLK circuit provides a low jitter, stable, high frequency
clock for use by the rest of the chip. The XOA and XOB pins
connect to the internal SYSCLK multiplier. The SYSCLK multiplier
can synthesize the system clock by connecting a crystal resonator
across the XOA and XOB input pins or by connecting a low
frequency clock source. The optimal signal for the system clock
input is either a crystal in the 50 MHz range or an ac-coupled
square wave with a 1 V p-p amplitude.
System Clock Period
For the AD9558 to accurately measure the frequency of incoming
reference signals, the user must enter the system clock period
into the nominal system clock period registers (Register 0x0103
to Register 0x0105). The SYSCLK period is entered in units of
nanoseconds (ns).
System Clock Details
There are two internal paths for the SYSCLK input signal: low
frequency non-xtal (LF) and crystal resonator (XTAL).
Using a TCXO for the system clock is a common use for the LF
path. Applications requiring DPLL loop bandwidths of less
than 50 Hz or high stability in holdover require a TCXO. As an
alternative to the 49.152 MHz crystal for these applications, the
AD9558 reference design uses a 19.2 MHz TCXO, which offers
excellent holdover stability and a good combination of low jitter
and low spurious content.
The 1.8 V differential receiver connected to the XOA and XOB
pins is self-biased to a dc level of ~1 V, and ac coupling is strongly
recommended. When a 3.3 V CMOS oscillator is in use, it is
important to use a voltage divider to reduce the input high
voltage to a maximum of 1.8 V. See Figure 34 for details on
connecting a 3.3 V CMOS TCXO to the system clock input.
The non-xtal input path permits the user to provide an LVPECL,
LVDS, 1.8 V CMOS, or sinusoidal low frequency clock for
multiplication by the integrated SYSCLK PLL. The LF path handles
input frequencies from 3.5 MHz up to 100 MHz. However,
when using a sinusoidal input signal, it is best to use a frequency
that is in excess of 20 MHz. Otherwise, the resulting low slew
rate can lead to substandard noise performance. Note that the
non-xtal path includes an optional 2× frequency multiplier to
double the rate at the input to the SYSCLK PLL and potentially
reduce the PLL in-band noise. However, to avoid exceeding the
maximum PFD rate of 150 MHz, the 2× frequency multiplier is
only for input frequencies that are below 75 MHz.
The non-xtal path also includes an input divider (M) that is
programmable for divide-by-1, -2, -4, or -8. The purpose of the
divider is to limit the frequency at the input to the PLL to less
than 150 MHz (the maximum PFD rate).
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the XOA and XOB input
pins. An internal amplifier provides the negative resistance
required to induce oscillation. The internal amplifier expects an
AT cut, fundamental mode crystal with a maximum motional
resistance of 100 Ω. The following crystals, listed in alphabetical
order, may meet these criteria. Analog Devices, Inc., does not
guarantee their operation with the AD9558 nor does Analog
Devices endorse one crystal supplier over another. The AD9558
reference design uses a 49.152 MHz crystal, which is high
performance, low spurious content, and readily available.
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
Fox FX3225BS
NDK NX3225SA
Siward SX-3225
Suntsu SCM10B48-49.152 MHz
SYSTEM CLOCK MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design with an
integrated VCO. It provides a means to convert a low frequency
clock input to the desired system clock frequency, fSYS (750 MHz
to 805 MHz). The SYSCLK PLL multiplier accepts input signals
of between 3.5 MHz and 600 MHz, but frequencies that are in
excess of 150 MHz require the system clock P-divider to ensure
compliance with the maximum PFD rate (150 MHz). The PLL
contains a feedback divider (N) that is programmable for divide
values between 4 and 255.
Pdiv
sysclk
Ndiv
sysclk
f
OSC
SYS
_
where:
fOSC
is the frequency at the XOA and XOB pins.
sysclk_Ndiv
is the value stored in Register 0x0100.
sysclk_Pdiv
is the system clock P divider that is determined by
the setting of Register 0x0101[2:1].
If the system clock doubler is used, the value of sysclk_Ndiv
should be half of its original value.
The system clock multiplier features a simple lock detector that
compares the time difference between the reference and feedback
edges. The most common cause of the SYSCLK multiplier not
locking is a non-50% duty cycle at the SYSCLK input while the
system clock doubler is enabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9557BCPZ | IC CLOCK TRANSLATOR 40LFCSP |
| V375C36M150BG | CONVERTER MOD DC/DC 36V 150W |
| AD9547BCPZ | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| D38999/20MF11JN | CONN RCPT 11POS WALL MNT W/SCKT |
| AD9549ABCPZ | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。