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參數(shù)資料
| 型號(hào)： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 54/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Data Sheet
AD9558
Rev. B | Page 53 of 104
IC SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I2C industry.
However, its disadvantage is programming speed, which is
400 kbps maximum. The AD9558 IC port design is based on the
IC fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a
glitch tolerance requirement on the control signals. That is, the
input receivers ignore pulses of less than 50 ns duration.
The AD9558 IC port consists of a serial data line (SDA) and a
serial clock line (SCL). In an IC bus system, the AD9558 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9558.
The AD9558 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9558 allows up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address that is
transmitted as part of an I2C packet. Only the device that has a
matching slave address responds to subsequent I2C commands.
Table 24 lists the supported device slave addresses.
I2C Bus Characteristics
Table 29. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
EE
Nonacknowledge
A
WEE
Write
R
Read
The transfer of data is shown in Figure 52. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
SCL
09758-
035
Figure 52. Valid Bit Transfer
Start/stop functionality is shown in Figure 53. The start
condition is characterized by a high-to-low transition on the
SDA line while SCL is high. The start condition is always
generated by the master to initialize a data transfer. The stop
condition is characterized by a low-to-high transition on the
SDA line while SCL is high. The stop condition is always
generated by the master to terminate a data transfer. Every byte
on the SDA line must be eight bits long. Each byte must be
followed by an acknowledge bit; bytes are sent MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The nonacknowledge bit (
AA
AEE
AA
) is the ninth bit attached to any 8-
bit data byte. A nonacknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
SDA
START CONDITION
STOP CONDITION
SCL
S
P
09758-
036
Figure 53. Start and Stop Conditions
1
2
8
9
1
2
3 TO 7
8
9
10
SDA
SCL
S
MSB
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
P
09758-
037
Figure 54. Acknowledge Bit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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