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參數(shù)資料
| 型號： | AD9558BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 64LFCSP |
| 產(chǎn)品變化通告： | AD9558 Minor Metal Mask Change 17/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9558
Data Sheet
Rev. B | Page 32 of 104
TDC/PFD
The phase-frequency detector (PFD) is an all-digital block. It
compares the digital output from the TDC (which relates to the
active reference edge) with the digital word from the feedback
block. It uses a digital code pump and digital integrator (rather
than a conventional charge pump and capacitor) to generate the
error signal that steers the DCO frequency toward phase lock.
Programmable Digital Loop Filter
The AD9558 loop filter is a third order digital IIR filter that is
analogous to the third order analog loop shown in Figure 37.
C3
C2
C1
R2
R3
09
758-
015
Figure 37. Third Order Analog Loop Filter
The AD9558 loop filter block features a simplified architecture
in which the user enters the desired loop characteristics directly
into the profile registers. This architecture makes the calculation
of individual coefficients unnecessary in most cases, while still
offering complete flexibility.
The AD9558 has two preset digital loop filters: high (88.5°) phase
margin and normal (70°) phase margin. The loop filter coefficients
are stored in Register 0x0317 to Register 0x0322 for high phase
margin and Register 0x0323 to Register 0x032E for normal phase
margin. The high phase margin loop filter is intended for
applications in which the closed-loop transfer function must
not have greater than 0.1 dB of peaking.
Bit 0 of the following registers selects which filter is used for
each profile: Register 0x070E for Profile A, Register 0x074E for
Profile B, Register 0x078E for Profile C, and Register 0x07CE
for Profile D.
The loop bandwidth for each profile is set in the following
registers: Register 0x070F to Register 0x0711 for Profile A,
Register 0x074F to Register 0x0751 for Profile B, Register 0x078F
to Register 0x0791 for Profile C, and Register 0x07CF to
Register 0x07D1 for Profile D.
The two preset conditions should cover all of the intended
applications for the AD9558. For special cases where these
conditions must be modified, the tools for calculating these
coefficients are available by contacting Analog Devices directly.
DPLL Digitally Controlled Oscillator Free Run Frequency
The AD9558 uses a Σ-Δ modulator (SDM) as a digitally controlled
oscillator (DCO). The DCO free run frequency can be calculated
from the following equation:
30
_
2
8
2
FTW0
f
SYS
freerun
dco
where FTW0 is the value in Register 0x0300 to Register 0x0303,
and fSYS is the system clock frequency. See the System Clock
section for information on calculating the system clock frequency.
Adaptive Clocking
The AD9558 can support adaptive clocking applications such as
asynchronous mapping and demapping. In these applications,
the output frequency can be dynamically adjusted by up to
±100 ppm from the nominal output frequency without manually
breaking the DPLL loop and reprogramming the part. This
function is supported for REFA only, not REFB.
The following registers are used in this function:
Register 0x0717 (DPLL N1 divider)
Register 0x0718 to Register 0x071A (DPLL FRAC1 divider)
Register 0x071B to Register 0x071D (DPLL MOD1
divider)
Writing to these registers requires an I/O update by writing
0x01 to Register 0x0005 before the new values take effect.
To make small adjustments to the output frequency, the user
can vary the FRAC1 and issue an I/O update. The advantage to
using only FRAC1 to adjust the output frequency is that the
DPLL does not briefly enter holdover. Therefore, the FRAC1 bit
can be updated as fast as the phase detector frequency of
the DPLL.
Writing to the N1 and MOD1 dividers allows for larger changes
to the output frequency. When the AD9558 detects that the N1
or MOD1 values have changed, it automatically enters and exits
holdover for a brief instant without any disturbance in the
output frequency. This limits how quickly the output frequency
can be adapted.
It is important to realize that the amount of frequency adjustment
is limited to ±100 ppm before the output PLL (APLL) needs a
recalibration. Variations that are larger than ±100 ppm are
possible, but the ability of the AD9558 to maintain lock over
temperature extremes may be compromised.
It is also important to remember that the rate of change in
output frequency depends on the DPLL loop bandwidth.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9559 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator |
| AD9559/PCBZ | 功能描述:時鐘和定時器開發(fā)工具 Multi-protocol line card dual clock RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| AD9559BCPZ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| AD9559BCPZ-REEL7 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Multi-protocol line card dual clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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