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參數(shù)資料
| 型號： | AD9895KBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 托盤 |
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REV. A
AD9891/AD9895
–37–
V
H
USE SEQUENCE 2
USE SEQUENCE 3
SEQUENCE 2 (OPTIONAL)
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 45. Example CCD Configuration
VERTICAL SHIFT
VERT SHIFT
SEQUENCE 1: VERTICAL BLANKING
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
CLPDM
DUMMY
INVALID PIXELS
INVALID PIX
CLPDM PULSE MAY BE USED DURING HORIZONTAL DUMMY PIXELS IF THE H-CLOCKS ARE USED DURING VERTICAL BLANKING.
Figure 46. Horizontal Sequences During Vertical Blanking
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 45 shows an example CCD layout. The horizontal regis-
ter contains 28 dummy pixels that will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9891/AD9895 horizontal signals for this
CCD, three sequences can be used. Figure 46 shows the first
sequence to be used during vertical blanking. During this time,
there are no valid OB pixels from the sensor, so the CLPOB and
CLPDM signals are not used. In some cases, if the horizontal
clocks are used during this time, the CLPDM signal may be used
to keep the AD9891/AD9895’s input clamp partially settled.
PBLK may be enabled during this time because no valid data is
available.
Figure 47 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loops of the AD9891/AD9895.
Figure 48 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB and CLPDM signals.
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| AD9895KBCZRL | 功能描述:IC CCD SIGNAL PROC/GEN 64-CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9898 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9898KCP-20 | 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS ANALOG FRONT END CONVERTE - Bulk 制造商:Analog Devices 功能描述: |
| AD9898KCPRL-20 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with Precision Timing⑩ Generator |
| AD9899ARS-2 | 制造商:Analog Devices 功能描述: |
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