參數(shù)資料
型號(hào)： AD9895KBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 56/58頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC/GEN 64-CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 64-VFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 64-CSPBGA（9x9）
包裝： 托盤
REV. A
AD9891/AD9895
–7–
AD9891 PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
AD9891
TOP
VIEW
(Not to Scale)
1234 567
9 10
8
A1 CORNER
INDEX AREA
PIN FUNCTION DESCRIPTIONS
1
Pin
Mnemonic Type2
Description
K9
VSG5
DO
CCD Sensor Gate Pulse 5
J9
VSG6DO
CCD Sensor Gate Pulse 6
K10
VSG7DO
CCD Sensor Gate Pulse 7
J10
VSG8
DO
CCD Sensor Gate Pulse 8
H10
H1
DO
CCD Horizontal Clock 1
H9
H2
DO
CCD Horizontal Clock 2
G10
HVDD
P
H1–H4 Driver Supply
G9
HVSS
P
H1–H4 Driver Ground
F10
H3
DO
CCD Horizontal Clock 3
F9
H4
DO
CCD Horizontal Clock 4
E10
RGVDD
P
RG Driver Supply
E9
RGVSS
P
RG Driver Ground
D9
RG
DO
CCD Reset Gate Clock
D10
CLO
DO
Reference Clock Output for
Crystal
C10
CLI
DI
Reference Clock Input
B10
TCVDD
P
Analog Supply for Timing Core
C9
TCVSS
P
Analog Ground for Timing
Core
A10
AVDD1
P
Analog Supply for AFE
B9
AVSS1
P
Analog Ground for AFE
A9
BYP1
AO
Analog Circuit Bypass
B8
BYP2
AO
Analog Circuit Bypass
A8
CCDIN
AI
CCD Signal Input
A7
BYP3
AO
Analog Circuit Bypass
B7
AVDD2
P
Analog Supply for AFE
B6
AVSS2
P
Analog Ground for AFE
A6
REFB
AO
Voltage Reference Bottom
Bypass
A5
REFT
AO
Voltage Reference Top Bypass
B5
SL
DI
3-Wire Serial Load Pulse
A4
SDI
DI
3-Wire Serial Data Input
B4
SCK
DI
3-Wire Serial Clock
A3
MSHUT
DO
Mechanical Shutter Pulse
B3
STROBE
DO
Strobe Pulse
B2
DVSS
P
Digital Ground
A2
DVDD
P
Digital Supply for VSG,
V1–V4, HD, VD, MSHUT,
STROBE, and Serial Interface
NOTES
1See Figure 50 for circuit configuration.
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
3In Register Readback Mode
4In Frame Transfer CCD Mode
Pin
Mnemonic Type2
Description
A1
VD
DO
Vertical Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
B1
HD
DO
Horizontal Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
C1
SYNCDIExternal System Sync Input
C2
LD/FD
DO
Line or Field Designator
Output
D1
DCLK
DO
Data Clock Output
D2
CLPOB/
DO
CLPOB or PBLK Output
PBLK
E1
NC
Not Internally Connected
E2
NC
Not Internally Connected
F2
DO/SDO
DO
Data Output (LSB)
(also Serial Data Output
3)
F1
D1
DO
Data Output
G2
D2
DO
Data Output
G1
D3
DO
Data Output
H2
D4
DO
Data Output
H1
D5
DO
Data Output
J2
D6
DO
Data Output
J1
D7
DO
Data Output
K2
D8
DO
Data Output
K1
D9
DO
Data Output (MSB)
K3
DRVDD
P
Data Output Driver Supply
K4
DRVSS
P
Data Output Driver Ground
J3
VSUB
DO
CCD Substrate Bias
J4
SUBCK
DO
CCD Substrate Clock
(E-Shutter)
K5
V1
DO
CCD Vertical Transfer Clock 1
J5
V2
DO
CCD Vertical Transfer Clock 2
K6
V3
DO
CCD Vertical Transfer Clock 3
J6
V4
DO
CCD Vertical Transfer Clock 4
K7
VSG1/V5DO
CCD Sensor Gate Pulse 1
(also V5
4)
J7
VSG2/V6DO
CCD Sensor Gate Pulse 2
(also V6
4)
K8
VSG3/V7DO
CCD Sensor Gate Pulse 3
(also V7
4)
J8
VSG4/V8DO
CCD Sensor Gate Pulse 4
(also V8
4)
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