參數(shù)資料
型號(hào): ADSP-2105BPZ-80
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/64頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 68PLCC
標(biāo)準(zhǔn)包裝: 19
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時(shí)鐘速率: 20MHz
非易失內(nèi)存: 外部
芯片上RAM: 3kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 738 (CN2011-ZH PDF)
ADSP-21xx
–34–
REV. B
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY WRITE
13 MHz
13.824 MHz 16.67 MHz
20 MHz
25 MHz
Parameter
Min
Max Min
Max
Min
Max
Min
Max
Min
Max Unit
Switching Characteristic:
tDW
Data Setup before WR High
25.5
23.2
17
12
7
ns
tDH
Data Hold after WR High
9.2
8.1
5
2.5
0
ns
tWP
WR Pulse Width
30.5
28.2
22
17
12
ns
tWDE
WR Low to Data Enabled
0
ns
tASW
A0–A13, DMS, PMS Setup before
9.2
8.1
5
2.5
1.5
1
ns
WR Low
tDDR
Data Disable before WR or RD Low
9.2
8.1
5
2.5
1.5
1
ns
tCWR
CLKOUT High to WR Low
14.2
29.2
13.1
28.1
10
25
7.5
22.5
5
20
ns
tAW
A0–A13, DMS, PMS, Setup before WR
35.7
32.2
23
15.5
8
ns
Deasserted
tWRA
A0–A13, DMS, PMS Hold after WR
10.2
9.1
6
3.5
1
ns
Deasserted
tWWR
WR High to RD or WR Low
33.5
31.2
25
20
15
ns
Figure 33. Memory Write
CLKOUT
A0 – A13
D
t
WR A
WR
DMS, PMS
t
WWR
t
WP
t
AS W
t
AW
t
CWR
RD
t
DH
t
DD R
t
WDE
t
DW
Frequency Dependency
(CLKIN
≤ 25 MHz)
Parameter
Min
Max
Unit
Switching Characteristic:
tDW
Data Setup before WR High
0.5tCK – 13 + w
ns
tDH
Data Hold after WR High
0.25tCK – 10
ns
tWP
WR Pulse Width
0.5tCK – 8 + w
ns
tWDE WR Low to Data Enabled
0
tASW
A0–A13, DMS, PMS Setup before WR Low
0.25tCK – 10
1
ns
tDDR
Data Disable before WR or RD Low
0.25tCK – 10
1
ns
tCWR CLKOUT High to WR Low
0.25tCK – 5
0.25tCK + 10
ns
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
0.75tCK – 22 + w
ns
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
0.25tCK – 9
ns
tWWR WR High to RD or WR Low
0.5tCK – 5
ns
NOTES
1For 25 MHz only the minimum frequency dependency formula for t
ASW and tDDR = (0.25tCK – 8.5).
w = wait states
× t
CK.
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