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參數(shù)資料
型號(hào): ADSP-2105BPZ-80
廠商: Analog Devices Inc
文件頁數(shù): 42/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 68PLCC
標(biāo)準(zhǔn)包裝: 19
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時(shí)鐘速率: 20MHz
非易失內(nèi)存: 外部
芯片上RAM: 3kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
ADSP-21xx
REV. B
–47–
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Frequency
10.24 MHz
Dependency
Parameter
Min
Max
Min
Max
Unit
Timing Requirement:
tBH
BR Hold after CLKOUT High1
29.4
0.25tCK + 5
ns
tBS
BR Setup before CLKOUT Low
1
44.4
0.25tCK + 20
ns
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
44.4
0.25tCK + 20
ns
tSDB
DMS, PMS, BMS, RD, WR Disable to BG Low
0
ns
tSE
BG High to DMS, PMS, BMS, RD, WR Enable
0
ns
tSEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
14.4
0.25tCK – 10
ns
NOTES
1If BR meets the t
BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the
ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
Figure 41. Bus Request/Grant
CLKOUT
PMS, DMS
BMS, RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
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