參數(shù)資料
型號: ADSP-21065LKSZ-264
廠商: Analog Devices Inc
文件頁數(shù): 15/44頁
文件大?。?/td> 0K
描述: IC DSP CONTROLL 544KBIT 208-MQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,串行端口
時鐘速率: 60MHz
非易失內(nèi)存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-MQFP(28x28)
包裝: 托盤
REV. C
ADSP-21065L
–22–
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (
BRx) or a host processor (HBR,
HBG).
Parameter
Min
Max
Unit
Timing Requirements:
tHBGRCSV
HBG Low to RD/WR/CS Valid1
20.0 + 36 DT
ns
tSHBRI
HBR Setup Before CLKIN2
12.0 + 12 DT
ns
tHHBRI
HBR Hold Before CLKIN2
6.0 + 12 DT
ns
tSHBGI
HBG Setup Before CLKIN
6.0 + 8 DT
ns
tHHBGI
HBG Hold Before CLKIN High
1.0 + 8 DT
ns
tSBRI
BRx, CPA Setup Before CLKIN3
7.0 + 8 DT
ns
tHBRI
BRx, CPA Hold Before CLKIN High
1.0 + 8 DT
ns
Switching Characteristics:
tDHBGO
HBG Delay After CLKIN
8.0 – 2 DT
ns
tHHBGO
HBG Hold After CLKIN
1.0 – 2 DT
ns
tDBRO
BRx Delay After CLKIN
7.0 – 2 DT
ns
tHBRO
BRx Hold After CLKIN
1.0 – 2 DT
ns
tDCPAO
CPA Low Delay After CLKIN
11.5 – 2 DT
ns
tTRCPA
CPA Disable After CLKIN
1.0 – 2 DT
5.5 – 2 DT
ns
tDRDYCS
REDY (O/D) or (A/D) Low from
CS and HBR Low4
13.0
ns
tTRDYHG
REDY (O/D) Disable or REDY (A/D) High from
HBG4
44.0 + 43 DT
ns
tARDYTR
REDY (A/D) Disable from
CS or HBR High4
10.0
ns
NOTES
1For first asynchronous access after
HBR and CS asserted, ADDR
23-0 must be a nonMMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when
HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.
2Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
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