參數(shù)資料
型號: ADSP-21065LKSZ-264
廠商: Analog Devices Inc
文件頁數(shù): 31/44頁
文件大?。?/td> 0K
描述: IC DSP CONTROLL 544KBIT 208-MQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機(jī)接口,串行端口
時鐘速率: 60MHz
非易失內(nèi)存: 外部
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-MQFP(28x28)
包裝: 托盤
REV. C
ADSP-21065L
–37–
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins. The delay and hold specifications given
should be derated by a factor of l.8 ns/50 pF for loads other
than the nominal value of 50 pF. Figure 28 and Figure 29 show
how output rise time varies with capacitance. Figure 30 shows
graphically how output delays and hold vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable time
under Test Conditions.) The graphs of Figure 28, Figure 29,
and Figure 30 may not be linear outside the ranges shown.
LOAD CAPACITANCE – pF
0
200
20
RISE
AND
FALL
TIMES
ns
40
60
80
100
120
140
160
180
2
RISE TIME
FALL TIME
4
6
8
10
12
14
16
18
Figure 28. Typical Rise and Fall Time (10%–90% VDD)
LOAD CAPACITANCE – pF
8.0
4.0
0
0200
20
RISE
AND
FALL
TIMES
ns
40
60
80
100
120
140
160
180
7.0
6.0
2.0
1.0
5.0
3.0
RISE TIME
FALL TIME
Figure 29. Typical Rise and Fall Time (0.8 V–2.0 V)
LOAD CAPACITANCE – pF
OUTPUT
DELAY
OR
HOLD
ns
5
–2
0
140
20
40
60
80
100
120
4
3
2
1
0
–1
160
180
200
6
Figure 30. Typical Output Delay or Hold
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