參數(shù)資料
型號(hào)： ADSP-21065LKSZ-264
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 43/44頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLL 544KBIT 208-MQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-MQFP（28x28）
包裝： 托盤
REV. C
ADSP-21065L
–8–
Pin
Type
Function
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21065L’s external bus. When
HBR is asserted in a multiprocessing system, the ADSP-21065L
that is bus master will relinquish the bus and assert
HBG. To relinquish the bus, the ADSP-
21065L places the address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins.
HBR has priority over all ADSP-21065L
bus requests (
BR
2-1) in a multiprocessor system.
HBG
I/O
Host Bus Grant. Acknowledges an
HBR bus request, indicating that the host processor may
take control of the external bus.
HBG is asserted by the ADSP-21065L until HBR is released.
In a multiprocessor system,
HBG is output by the ADSP-21065L bus master.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-21065L.
REDY (O/D)
O
Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait states to an asyn-
chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by
default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D).
REDY will only be output if the
CS and HBR inputs are asserted.
DMAR
1
I/A
DMA Request 1 (DMA Channel 9).
DMAR
2
I/A
DMA Request 2 (DMA Channel 8).
DMAG
1
O/T
DMA Grant 1 (DMA Channel 9).
DMAG
2
O/T
DMA Grant 2 (DMA Channel 8).
BR
2-1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065Ls to arbitrate for bus
mastership. An ADSP-21065L drives its own
BRx line (corresponding to the value of its ID
2-0
inputs) only and monitors all others. In a uniprocessor system, tie both
BRx pins to VDD.
ID1-0
I
Multiprocessing ID. Determines which multiprocessor bus request (
BR
1–BR2) is used by
ADSP-21065L. ID = 01 corresponds to
BR
1, ID = 10 corresponds to BR2. ID = 00 in single-
processor systems. These lines are a system configuration selection which should be hard-wired
or changed only at reset.
CPA (O/D)
I/O
Core Priority Access. Asserting its
CPA pin allows the core processor of an ADSP-21065L
bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an
open drain output that is connected to both ADSP-21065Ls in the system. The
CPA pin has an
internal 5 k
W pull-up resistor. If core access priority is not required in a system, leave the CPA
pin unconnected.
DTxX
O
Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 k
W internal pull-
up resistor.
DRxX
I
Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 k
W internal pull-up
resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
W internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
W internal pull-up resistor.
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
BSEL
I
EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured for booting from
an 8-bit EPROM. When BSEL is low, the BSEL and
BMS inputs determine booting mode. See
BMS for details. This signal is a system configuration selection which should be hardwired.
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